MCLKIN & BCLK synchrony in ADAU1701


I'm try to design an I2S communication system with a uC and ADAU1701.

uC has to be master in I2S and obtain the digital audio from ADAU1701.

ADAU1701 has an crystal of 12.288MHz as source clock, because fs=48KHz.

In order to use Audio Digital Output from ADAU1701, the clock signal MCLKIN of dsp and BCLK from I2S master, needs to be synchronous.

How do i reach synchrony between MCLKIN of ADAU1701 and BCLK from uC?



  • Hi TylerK, thank you very much!

    The clock frequency of uC is 40MHz. The problem is that the uC is part of an integrated module, so I can't access to this clock source.

    The PLL settings in the 1701 are PLL_MODE0=0 , PLL_MODE1=1.

    Any ideas?

  • Hello,

    What is the clock frequency of your uC? It may be possible to use the uC as an external MCLK for the ADAU1701 -- depending on the PLL settings of the 1701, there is some flexibility for the MCLK frequency input.



  • My pleasure!

    I just tested out something that should work as a solution to your problem. Assuming your BCLK is 3.072 MHz (which it should be, for 48kHz I2S), you can actually use that as your MCLK!

    To do so, you'll need to set PLL0 and PLL1 both to 0. Then, route the BCLK signal to both the INPUT_BCLK and the MCLKI pins. Just be sure that the BCLK will always be running, or the 1701 will stop

    The reason this works is because setting PLL0 and PLL1 both to 0 tells the ADAU1701 to expect an MCLKI signal that is 64*fs. For I2S, this is the same frequency as the BCLK.

    Hope this helps,


  • Hi TylerK,

    I made the necessary changes to set PLL0=0 and PLL1 =0, and route BCLK signal from uC to BCLK (MP11) and MCLKIN in 1701. So I have an issue in my uC, i can't set a BCLK to 3.072MHz, the max frequency is 1.4112MHz.

    Here is my proposal:

         Change the fs=44100 in order to set an I2S BCLK signal 44100*16bits*2channel=1.4112MHz.

         Can I configure 1701 to expect an MCLK signal 32*fs?

    In page 18 of 1701's datasheet, appear:

    "If the ADAU1701 is set to receive double-rate signals (by reducing the number of program steps per sample by a factor of 2 using the core control register), the master clock frequency must be 32 × fS, 128 × fS, 192 × fS, or 256 × fS. If the ADAU1701 is set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the core control register), the master clock frequency must be 16 × fS, 64 × fS, 96 × fS, or 128 × fS."

    What does "double-rate" and "quad-rate" mean?

    Thank you for your help!


  • 0
    •  Analog Employees 
    on Jun 8, 2016 6:05 PM

    Hello JGA,

    It means that the core will run at double the "normal" rate or four times the rate. It reduces the number of instructions per sample period but allows the core to run at a faster sample rate.

    The problem with your calculation is that you cannot run this part in packed mode for the serial data. Standard I2S has 32 bits per channel so it has 64 bits per frame. So therefore the BCLK must be 64x fs.

    It seems to me that your choice of uC is too limiting. If it cannot produce a BCLK for an I2S signal at 48k fs (or 44.1) then it will not be able to do much processing of the audio data at that rate. I assume you are just passing audio through the uC so perhaps not much needs to be done, the DSP will do most of that I suppose. So then why do you need to run audio through the uC. Usually I see the uC only serving to control and direct the audio stream and not be in the signal chain. So maybe fill us all in on your application?

    Dave T