Serial Port Clock Domains in ADAU1450


In ADAU1450, Do we require seperate clock domains (LRCLK and BCLK) for each Serial data input and output?

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  • Just found this post after several days of searching. Had been pulling my hair out over this...

    Seeing the exact bug described on a board I designed. I am using port 0 as output, with LRCLK and BCLK both as master. I set port1 to slave from clk domain 0, and get no data out. If I select LRCLK to master it works. 

    Assume this bug is still present as was said 4 years ago?

    Does this bug affect BCLK as well, i.e. should this also be set to master on port 1 to ensure it works properly? Or does the ADAU1452 not care about BCLK?

    Thanks in advance.

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  • Just found this post after several days of searching. Had been pulling my hair out over this...

    Seeing the exact bug described on a board I designed. I am using port 0 as output, with LRCLK and BCLK both as master. I set port1 to slave from clk domain 0, and get no data out. If I select LRCLK to master it works. 

    Assume this bug is still present as was said 4 years ago?

    Does this bug affect BCLK as well, i.e. should this also be set to master on port 1 to ensure it works properly? Or does the ADAU1452 not care about BCLK?

    Thanks in advance.

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