ADAU1701
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The ADAU1701 is a complete single-chip audio system with a 28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like control interfaces. Signal processing...
Datasheet
ADAU1701 on Analog.com
Hi
My customer is trying to initiate an i2c read from adau1701.
Addr0==Addr1=0 => Write addr = 0x68, Read addr = 0x69.
Sequence looks like he indeed sends 0x69, however adaqu1701 doesn't send an ack (pulls SDA low on 9th clock)
Attached are read sequence & schematics.
Similar write sequence (sending 0x68) produces the required ack.
Please advise
BR,
Alon
Hello Dave
Thanks for the detailed answer.
The main point is the missing ACK from the ADAU1701 device, if we look closly at fig 21 the first frame ends with such an ACK (which the I2C master would sample on the 9th rising edge of SCL). That is before we can continue with the additional frames of the exact register address inside the ADAU1701.
In other words, the first frame is to select teh ADAU1701 on the I2C bus, with the next 2 frames to select the exact ADAU1701 register . This is true for both read and write operations. the rest of the frames differ between read/write operations. Only on frame 4 you send a repeated start condition. The waveform indicates that the master sent a stop condition as it got a NACK. I believe that this was the right responce.
The same first frame with a write operation resulted in the ADAU1701 sending the required ACK.
I will try to check if the timing is marginal and is the culprit.
Is there anything we're missing?
Does the ADAU1701 needs an initial write before a read?
Thanks
Alon
Hello Dave
Thanks for the detailed answer.
The main point is the missing ACK from the ADAU1701 device, if we look closly at fig 21 the first frame ends with such an ACK (which the I2C master would sample on the 9th rising edge of SCL). That is before we can continue with the additional frames of the exact register address inside the ADAU1701.
In other words, the first frame is to select teh ADAU1701 on the I2C bus, with the next 2 frames to select the exact ADAU1701 register . This is true for both read and write operations. the rest of the frames differ between read/write operations. Only on frame 4 you send a repeated start condition. The waveform indicates that the master sent a stop condition as it got a NACK. I believe that this was the right responce.
The same first frame with a write operation resulted in the ADAU1701 sending the required ACK.
I will try to check if the timing is marginal and is the culprit.
Is there anything we're missing?
Does the ADAU1701 needs an initial write before a read?
Thanks
Alon