I have an application where the ADAU1701/2 would be ideal, but the lack of bit shift will be a problem, I have 2 input streams with each stream being audio packed as four 12 bit numbers (2x 12bit left and 2x 12bit right) I need to de-multiplex these and re-multiplex them as 2 x outputs streams.
I am wondering if there is any way of preserving the sign bit from the lower 12 bits?
Any help would be appreciated
It might be done graphically, although it seems to be a job better done by a consultant for a stand alone, specific module created for your application. This type of processing, is one of those things not easily done graphically, since it really is about splitting words. Graphical programming is better used for processing atomic streams (although there are exceptions).
Would you consider a consultant or would you rather try this with existing blocks.
As AD don't give access to assembler I guess I would like to do it graphically, I don't like using consultants when I can usually (with a few pointers) do the dsp.
Its trying to get my head around the blocks graphically, and how the blocks work. My current design is based on TI and a cpld, but I could do it in a single ADAU1701
any pointers would be appreciated.
I had to take this on as a challenge to do it with standard cells. I think this will work but it is difficult to test this using a DC cell as a source. So give it a try.
Here is what I did...
This circuit above will take my DC cell for input and I am looking at it two ways. You probably know this but I will explain this here for others. The ReadBack mechanism in the ADAU1701 is only 24 bits wide. In the DSP core you have 28 bit wide data. So the ReadBack only displays the top 24 bits leaving the bottom four bits truncated. This is often not an issue except when you need to look at indexes that start with 1. So you have to multiply by 16 to be able to see the bottom nibble. The other detail is that since the gain cells use a 5.23 number, and the top bit is the sign bit, you cannot input a 16, so you multiply by 4 twice.
Next I am multiplying by 1/64 twice. This will shift out the bottom 12 bits out into the bit bucket leaving only the original upper 12 bits.
Then you see I have some readback cells to help me look at it to verify the data.
Then I multiply by 4 six times to get the 12 bits shifted back up to where they started minus the bits that fell into the bit bucket.
Then I take this upper 12 bits and subtract them from the incoming muxed data leaving only the lower 12 bits.
Then I multiply by 4 six times to bring it up to the upper 12 bit position.
So then I have two 12 bit numbers successfully separated and ready to send to the output ports.
In my project I have them assigned to the outputs.
So I could not properly test this so let me know if this works. It does use a lot of cells but I limited it mostly to multiplies which are more efficient.
All the readbacks can obviously be deleted.
I attached the project.
Thanks for this
I've just got back in the office so I will go through it. my worry was preserving the sign of the shifted bits and I can test this with the dc and views.
Once again thank you for doing this, I think I will try a board with these parts on and see how it goes.
Can you tell me how the 24 bit sample is stored in the accumulator? $7FF is the largest positive number, but how is this expressed in the sample 5.23 register?