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ADUA1462 Program and Data memory size

		
		

		

			

									
						Paramecium
					
							

			
				
									
											
			        
                                                			
				
			
		


				
		

		    
		    
		    		    
			
Hi,

 
Please let me confirm memory size of the ADAU1462.

 
On the ADI web page and data sheet ( rev.A ), we can find below. Is it correct values ?

 
http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1462-1466.pdf 

 
  Page 3 Table1. Product Selection Table
  ADAU1462 Data memory 48(KWords) Prgram Memory 16(Kwords)

 

But on the data sheet ( rev.A ), we can find different values.
The table 58 shows that ADAU1462's program memory size is 8 Kwords
It seems that the Figure 82 for the ADAU1466 illustrates the ADAU1462, but the program memory size is 8K words
It seems that the Figure 83 for the ADAU1462 illustrates the ADAU1466.

 
  Page 88 Table 58. ADAU1462 Memory Map
  Address Range         Length
  0xC000 to 0xCFFF      4096 words
  0xC000 to 0xCFFF      4096 words

 
  Page 89 Figure 82. ADAU1466 Slave Port Memory Map and the Mapping onto the SigmaDSP Core Memory
  Page 90 Figure 83. ADAU1462 Slave Port Memory Map and the Mapping onto the SigmaDSP Core Memory

 
On the other hands, on the Sigma Studio ver3.15.2 beta,
when putting the ADAU1462 in the project and build the schematic, we can see following messages.
The data program size is 40 Kwors.

 
###### IC 1 ######
ADAU145X Assembler, Analog Devices Inc.
Version: 3.15.2,1721  (built 6/29/2017)

 
##### Compile Started: Thursday, October 12, 2017 7:03:52 PM #####
##### Compile succeeded:  0 errors, 0 warnings #####

 
##### Summary #####
DM0 RAM used:       00024    (of 20480)
DM1 RAM used:       00013    (of 20480)
PM  RAM used(Data): 00000    (of 16384)
PM  RAM used(Inst): 00083    (of 16384) 71 instructions (32bit: 59  64bit: 12)
Total PM used:      00083    (of 16384)

								


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	

		
	











	

	

					



			








	
	
	
	



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    Thanks for your response.
    
 
    Regarding the compiler, I put the ADAU1462 in the Sigma Studio Ver. 3.15 Build 3, Rev 1741.
    
 
    How we should change the data memory size on the Sigma Studio, I would like to know.
    
 
    Please find attached test data.
    
 
    Regarding the data sheet, I had found two more things. ( If I should write them in other thread, I will do so ).
    
 
    1. SPI port timing chart / Depending on the page, the SCLK signal level is different during the SS is high ( unselected ).
    
 
    On Page 42, the data sheet says "The format for the SPI communications slave port is commonly known as SPI Mode 3".
    
 
    And "Figure 36. Clock Polarity and Phase for SPI Slave Port" shows that the SCLK is high during the SS is high.
    
 
    On Page 14, "Figure 8. SPI Slave Port Timing Specifications shows that  the SCLK is low during the SS is high
    
 
    2. Control Register description
    
 
    On page 92 - 97 Table 59. Control Register Summary, the "0xF899  SECONDPAGE_ENABLE" and "0xF890    SOFT_RESET", the order of these registers is reversed.
    
 
    Around page 196, there are not descriptions about the "0xF899  SECONDPAGE_ENABLE".
    
			
    

		
		
		
				ss315_adau1461_test01.zip
			
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    

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													0
							
			
				
									
							
						
				
			
					
    
	
    

		
		
    
					
    Thanks for your response.
    
 
    Regarding the compiler, I put the ADAU1462 in the Sigma Studio Ver. 3.15 Build 3, Rev 1741.
    
 
    How we should change the data memory size on the Sigma Studio, I would like to know.
    
 
    Please find attached test data.
    
 
    Regarding the data sheet, I had found two more things. ( If I should write them in other thread, I will do so ).
    
 
    1. SPI port timing chart / Depending on the page, the SCLK signal level is different during the SS is high ( unselected ).
    
 
    On Page 42, the data sheet says "The format for the SPI communications slave port is commonly known as SPI Mode 3".
    
 
    And "Figure 36. Clock Polarity and Phase for SPI Slave Port" shows that the SCLK is high during the SS is high.
    
 
    On Page 14, "Figure 8. SPI Slave Port Timing Specifications shows that  the SCLK is low during the SS is high
    
 
    2. Control Register description
    
 
    On page 92 - 97 Table 59. Control Register Summary, the "0xF899  SECONDPAGE_ENABLE" and "0xF890    SOFT_RESET", the order of these registers is reversed.
    
 
    Around page 196, there are not descriptions about the "0xF899  SECONDPAGE_ENABLE".
    
			
    

		
		
		
				ss315_adau1461_test01.zip
			
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

    

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