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ADAU1467 SDATA IO not working

We are using the ADAU1467 with the additional SDATA input lines for our ADCs but we cannot get a working configuration for the IOs.

Is this feature even yet implemented?

Sigma Studio 3.16B1R1744 in use

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  • There has been some confusion about my answers above, so I will try to summarize:

    • There is only one use-case that requires a hardware workaround, and it is when all of the following are true
      1. The serial port is an input
      2. The port is in stereo mode (I2S, LJ or RJ)
      3. The SDATAIO pins are being used to receive additional stereo input on the same port
      4. The port is operating as a BCLK clock master

    If all of these are true, then either the BCLK or the LRCLK must be generated from another pin.

    • If 1, 2, and 3 are true, but the stereo input port is operating as a clock slave, select TDM4 mode instead of stereo mode, and everything will work as expected.
    • All other modes, including stereo modes on the outputs and TDM8, work as described in the data sheet.

    : You are seeing a user interface bug in version 3.16 of SigmaStudio. The mode you need works with no problems on the silicon. The GUI should not show that this is an invalid mode. If you have any problems making this work, please let me know.

    Ken

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  • There has been some confusion about my answers above, so I will try to summarize:

    • There is only one use-case that requires a hardware workaround, and it is when all of the following are true
      1. The serial port is an input
      2. The port is in stereo mode (I2S, LJ or RJ)
      3. The SDATAIO pins are being used to receive additional stereo input on the same port
      4. The port is operating as a BCLK clock master

    If all of these are true, then either the BCLK or the LRCLK must be generated from another pin.

    • If 1, 2, and 3 are true, but the stereo input port is operating as a clock slave, select TDM4 mode instead of stereo mode, and everything will work as expected.
    • All other modes, including stereo modes on the outputs and TDM8, work as described in the data sheet.

    : You are seeing a user interface bug in version 3.16 of SigmaStudio. The mode you need works with no problems on the silicon. The GUI should not show that this is an invalid mode. If you have any problems making this work, please let me know.

    Ken

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  • To add additional clarification, please note that if the following are true:

    1. The serial input is receiving stereo data (I2S, LJ, or RJ)
    2. The serial input port is a clock slave
    3. LRCLK is a 50/50 duty cycle clock

    The serial input port must be configured as a TDM4 input, and data will appear on even numbered channels (0/2/4/6/8/10, etc). No data will be lost as a result of this change.

    Additionally, if the external clock master is functioning exactly as the DSP is configured, you may change the "LRCLK Type" to Pulse (even though it's actually being received as 50/50) and data will appear on the standard channels (0/1/4/5/8/9, etc) and can be passed through ASRCs in stereo pairs.

    Please see this post for more detail:

    https://ez.analog.com/audio/f/q-a/122099/sdataio-is-not-working-correctly-of-adau1463/363509#363509

    Joshua