ADAU1701 / ADAU1401 SPI Interface Timing

The ADAU1701 and ADAU1401 data sheets specify maximum SPI clock CCLK frequency as 6.25MHz.

The data is available on the COUT pin up to 101ns after the CCLK falling edge according to the table above, but the Figure 3 below clearly shows this delay as specified from CCLK rising edge.

The data sheet also states that: "COUT data is shifted out of the ADAU1401A on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on the CCLK rising edge."

For 6.25MHz clock with 50% duty cycle there is 80ns from falling clock edge to the rising edge. How the SPI interface could work with up to 101ns delay of the CDATA from the CCLK falling edge with the data being sampled by the microcontroller on the clock rising edges? Is the delay value correct?

According to the SPI timing diagrams either SPI mode 0 (CPOL = 0, CPHA = 0) or mode 3 (CPOL = 1, CPHA = 1) could be used for the ADAU1701 / ADAU1401 SPI accesses.

Could Analog Devices confirm the above.

  • 0
    •  Analog Employees 
    on Feb 13, 2018 8:47 PM

    Hello Les_K,

    The diagram has the extension lines shown incorrectly. The data always changes on the falling edge of the clock and is read by the master on the rising edge. So the Cout would be changing on the falling edge. The description in the table is correct.

    Now you are correct that it appears that the worst case over all temperatures and all silicon skews, plus a safety margin, that the SPI clock frequency may need to be lower when reading from the part. It appears that when reading the max should be around 4.95 Mhz. When writing to the part it will still be the 6.25Mhz max but reading appears to be slower due to the delay of the Cout data being ready.

    It would be difficult to open up all the characterization data and look back to see if this was simply an error in the specifications or if it is correct. This part is an older part at this point.

    Dave T

  • Hi Dave,

    Sorry for my delayed response.

    Yes, it appears that the maximum clock speed for SPI writes is higher than for SPI reads due to the COUT pin delay of 101ns maximum from the CCLK falling edge.

    We have certainly experienced read data errors when trying to use 6MHz SPI clock for writes and reads. Lowering the SPI clock frequency solved this issue.

    Regards,

    Les