ADAU1466 Serial Port 2 Configuration

I am looking for assistance with setting up Serial Input Port 2 as an I2S input using SigmaStudio 3.17.  I have created a project with a Input block with channels 32-33 selected.  This connects to a two channel volume control and then to two outputs.  The project link, compiles and downloads without problem and the volume control is working.  However, instead of Serial Port 2 accepting I2S signals as inputs, it is sending out Bclk and LRclk clock signals.  Looking at the ADAU1466 data sheet, pins 65-67 (Serial Port 2 pins) are bidirectional and must be configured.  Obviously, the project I have desinged with SigmaStudio is not properly configuring these pins. 

  • +1
    •  Analog Employees 
    on May 4, 2018 12:04 AM over 2 years ago

    Hello Mystic12,

    You need to set up those pins to be slaves not masters. You have a choice as far as which of the four output pots pins it is slaving to. I will assume you have the external device connected to the LRCLK and BCLK pins for serial output port 2. So then you need to click on the pull down box and select clock domain 2.

    This is located on the hardware register settings tab under the Serial Port sub-tab.

    Here is a screenshot.

    You have to set this on both the LRCLK and BCLK panels.

    Dave T

  • Dave,

    Thank you for the reply to my question.  I can see from the screens that you included and your description of what I need to do that you understand my question and know the answer.  Frustratingly, however, I have searched all over SigmaStudio 3.17 and I cannot find the "hardware register settings tab under the Serial Port sub-tab" that you reference.  I apologize for my ignorance, but after checking everywhere on the screen, the Toolbox, and after checking the options and settings for the cell in my design "Input1" (which has channel 32-33), I cannot find what you are talking about.  I also went back through everything I could find in the toolbox to see if there is such a thing as "Serial Input Port 2", but all I can find as a possible "input" in the toolbox is "I/O", "Input", "Sdata 32-39", "Input".  I am using this as the input in my schematic (as you can see from the project I attached).   Resigned to my embarrassment when shown the "answer", I must "give up" and ask for further explanation as to how you locate the items you reference. Lol.

    Thank you!


  • 0
    •  Analog Employees 
    on May 7, 2018 1:59 AM over 2 years ago

    Hi. To get to the window to set the registers that Dave described, Click on the "Hardware Configuration" tab at the top of the main window:

    Then, at the bottom of that window, click on the tab for the IC that you want to configure. In this case, it is the "IC 1 - ADAU1466 Register Controls" tab:
    Going back up to the top of the window, you'll see a set of tabs that show the register setting for each section of the processor. You want the Serial Ports:
    Hope this helps,
  • 0
    •  Analog Employees 
    on Feb 14, 2020 9:26 AM over 1 year ago in reply to DaveThib

    Hi Dave,

        I notice that the serial input port and serial output port both have the menu selection" slave from CLK domain x". what makes me confuse is that if I configure both the serial input port0 and serial output port0 to the "slave from CLK domain 0", are they slave to the same CLK domain?

        what should I understand the CLK domain here?



  • 0
    •  Analog Employees 
    on Feb 14, 2020 6:16 PM over 1 year ago in reply to Yosen

    Hi Yosen,

    "CLK domain 0" on the serial inputs is NOT the same as "CLK domain 0" on the serial outputs.

    Although the serial ports on the ADAU1466 are very flexible, one of their limitations is that you cannot easily share clock domains between input and output ports. You can get around this most easily by wiring LRCLK and BCLK to both the input and output clock pins on the DSP.

    For example, let's say that I am using Serial Input Port 2 as clock slave to another source. I also want Serial Output Port 2 to be a slave to that same source.

    In this case, I need to connect LRCLK_IN2 and BCLK_IN2 to the clock master and set the LRCLK and BCLK source to "Slave from CLK domain 2" for the input port. I also need to connect LRCLK_OUT2 and BCLK_OUT2 to the clock master and set the LRCLK and BCLK source to "Slave from CLK domain 2" for the output port.

    Does that answer your question?