Help with ADAU1466 + XU316 USB Transport + Dual PCM5102A DACs (High Sample Rate / Low Noise Setup)

Hello Zbotnik,

Well,.... I had designed a board using an XMOS USB interface into a SigmaDSP way back in 2015-ish...  It worked well. I just cracked open the schematic to remind myself of a few details. 

First let me answer a few of your questions. The ADAU1466 can be setup to operate in 32-bit mode for the serial input and output ports. It is a matter of a few register settings. These details we can discuss later and there may be a few examples on the forum. 

For sample rate? This is a personal preference for sure. I think 96kHz is a good balance between added fidelity and still have plenty of instructions available. At 48k you get 6,144 instructions. So at 96kHz fs you get 3,072 instructions assuming the PLL is properly setup of course. 

It is still a decent amount of instructions. However, with your application I do not think you will need a huge amount of instructions so you might be fine running at 192kHz. The only problem is that you will run into issues sending these high frequency clocks over jumper wires between boards. I STRONGLY suggest you start at 48kHz fs. Get it all to work then bump up the sample rate to 96kHz, get that to work and then 192kHz. I will be surprised if you can get 192kHz to work using jumper wires and eval boards. You have some tools to help like adjustable drive strength on outputs but that only gets you so far. 

Ok, clocking... For my design I used a PLL to develop the MCLK for the XOMS and the DSP. I also used a distribution amp to get one destination for each output. I forget what the frequency was but it should most likely be 12.288MHz. I think the XMOS can deal with that. 

My suggestion is to get it working first at a low sample rate and 24 bits. Then go from there. 

I did use a sample rate converter on the DSP but I also had experimented with synching the DSP core to the incoming sample rate from the XMOS so the ASRC would not be needed.  This gets tricky with the DAC. This means the DAC also needs to be clocked from the XMOS. So the XMOS LRCLK and BCLK outputs would have to go to three places, the DSP input serial ports, the DSP output serial ports and then the DACs. This will be super hard to do at 192kHz. You may need to use a distribution amp for those clocks too!

But, sonically, this should be the best. No sample rate converters involved. 

Well, these are my first thoughts. 

Will this be a product at some point? 

Dave T

Thanks again for the detailed reply, it helped me get a lot further. I was able to get the XU316 feeding a solid 96 kHz LRCK into the ADAU1466 and also confirm 96 kHz on the outputs. Running 32-bit at 96 kHz, I avoided needing the ASRC by setting Clock Gen 3 to do the math for 96 kHz, and everything works the way you’d expect — crossovers line up correctly and the 80 Hz lowpass behaves as it should.

Where I’m stuck is when I try to push it to 192 kHz. If I change the arithmetic on Clock Gen 3 and set the core to 192 kHz, the crossovers act strange. My 80 Hz lowpass goes from a normal -3 dB point to about -12 dB at 80 Hz. Any idea why the filters scale like this when moving from 96 kHz to 192 kHz, and what the right way would be to fix it?

Edit: Sorry, I forgot to add that this is just a personal project.

Hey, I just want to say thank you for the lengthy reply. I really appreciate you taking the time to answer my questions.

After spending some time trial-and-erroring my way through the settings, I finally managed to get everything working the way I had originally intended when I started this project (woo)!

I have the XU316 audio transport sending 32-bit, 192 kHz I²S into the ADAU1466’s serial input. The serial input is set to 32-bit, I²S, 2-channel. I’m taking the LRCLK and BCLK directly from the XU316, leaving the sampling rate at default since slave mode bypasses it.

For the serial outputs, I have them set the same way except with the ADAU1466 as Master on the output side. This feeds my PCM5102As, and I set the sample rate source to Clk1 ×4, which gives me 192 kHz on the outputs. I also set the DSP project sample rate to 192 kHz. Then in Clock Control, I set the Start Pulse Selection to Base_Fs ×4. This makes the DSP core itself run at 192 kHz and fixed the issue I was having where the filters only worked correctly at 48 kHz.

Next, I went into the ASRC section of the Routing Matrix and set ASRC0 as follows:

• Input Feed: Serial Input 0/1

• Source: Serial Input

• Output Rate: DSP Source (so the output is synced to the DSP clock)

From there I built a simple high-pass/low-pass setup for my home system (bookshelf speakers and a sub). I wired the ASRC input blocks to the appropriate outputs, which for me ended up being 0/1 and 16/17 — those are the first left and right channels on SDATA_OUT0 and 1. After verifying with the scope that the input/output were metering as expected, I added the crossovers. They worked exactly as they should: on a Butterworth low-pass I now get −3 dB at cutoff, textbook behavior for this type of crossover.

My takeaway is that keeping the ASRC input block instead of the raw serial input block guarantees the clocks are asynchronous. Beyond that, I didn’t notice any difference in actual audio between using SDATA Input directly versus going through the ASRC.

TL;DR: If your ADAU1466 filters don’t behave correctly at 192 kHz, make sure your project sample rate is set to 192 kHz and your Start Pulse Selection in Clock Control is set to Base_Fs ×4. That’s what finally fixed it for me.

Hello Zbotnik,

Yes, setting the sample rate is a three legged chair. Set SigmaStudio to the correct fs so it generates the proper code, set the DSP start pulse to the correct clock source and then set the serial ports to the correct rate. 

The ASRCs do work well and sound good. However, I am wondering if you might be able to do with out them? What is the situation with master clock? Are the DSP, the ADC and the DACs all running on the same master clock? If they are then you will not need to use the ASRC. 

Dave T

Hello Dave,

I have ASRC0 working at 192 kHz, but the system also runs fine without it. To get ASRC0 to lock, I had to set the Output Rate to 1 FS ×4, and it’s been stable since.

My concern is that the XU316 transport and ADAU1466 DSP core are both running at 192 kHz but not synchronized. Would this cause clock drift over time? If not, I’d prefer to remove ASRC0 to avoid the extra latency in the chain.

Do you recommend tying the XU316 and ADAU1466 to a shared MCLK to avoid any possible drift?

Are there measurable tradeoffs in distortion, noise, or jitter when using ASRC versus direct synchronous input at 192 kHz?

Are there known limitations when running the ADAU1466 at 192 kHz, such as reduced block availability or filter accuracy?

I really appreciate your time and guidance on this — thank you for helping me work through these details.

Best regards,
Zachary

Hello Zachary,

Provided the correct MCLK is being provided and the PLL is correctly setup...  For instance, a 12.288MHz crystal/MCLK Source, will be multiplied to obtain the 294.912MHz internal system clock. 

This is the instruction clock. So if you are running at 48kHz you will have 294,912,000 / 48,000 = 6,144 instructions per sample period. 

So if you are running at 192kHz the number of instructions per sample period is 1,536. Much fewer instructions available. 

It will not affect the filter accuracy at all but you cannot have as many filters or really long FIR filters. 

Regarding the MCLK. If the ADC is running on a different MCLK, the rates will never be the same. They may be close enough but occasionally samples will either be missed or repeated. If it is not too many samples then it can be difficult to hear. 

The same thing goes for the DACs. They also need to be running from the same MCLK. 

Dave T

Hello Zachary,

Provided the correct MCLK is being provided and the PLL is correctly setup...  For instance, a 12.288MHz crystal/MCLK Source, will be multiplied to obtain the 294.912MHz internal system clock. 

This is the instruction clock. So if you are running at 48kHz you will have 294,912,000 / 48,000 = 6,144 instructions per sample period. 

So if you are running at 192kHz the number of instructions per sample period is 1,536. Much fewer instructions available. 

It will not affect the filter accuracy at all but you cannot have as many filters or really long FIR filters. 

Regarding the MCLK. If the ADC is running on a different MCLK, the rates will never be the same. They may be close enough but occasionally samples will either be missed or repeated. If it is not too many samples then it can be difficult to hear. 

The same thing goes for the DACs. They also need to be running from the same MCLK. 

Dave T