No I2S output

Question

I have a custom board with a ADAU1362 fitted. This is linked to a separate satellite modem, that is the mister/main. The modem generates the WS (8KHz sample rate) and SCK (512KHz), expecting 16-bit data. A Microchip pic is connected by I2C to the CODEC to program the registers. I have an 8MHz clock feeding the CODEC, which I use with the PLL. 
 I cannot see any data coming out of the CODEC. I watch the WS and SCK lines which are OK, but the data lines are permanently low. 
 I can read and write the I2C OK, the PLL does lock. 
 I am feeding a 1KHz sine wave into LINN. I enable LINNG, I enable Mixer1, I enable MX3G1, I enable Mixer 3, I enable LHPVOL, I enable MX3LM, I enable MX5G3, I enable Mixer 5, I enable LOUTVOL. I enable the ADC. 
 I also cannot see any direct feed through from LINN to LHP or LOUTP. 
 I am stuck. Can someone give me some register settings that work, or suggest a method to debug this. 
 I am using an oscilloscope and a Saleae Logic device to look at the outputs.

DaveThib · Accepted Answer

Hello Konradb, 
 
 I am assuming you have an ADAU1361 since we do not make an ADAU1362. This would be a good part for this application so I think it is a 1361. 
 You may have an issue with frequencies. 
 We have to be exact here. 
 If the modem is sending the sampling rate clock and the bit clock then is it also sending the MCLK to the codec? You mentioned 8MHz but failed to mention where it comes from? 
 
 These older parts worked a little differently than the more modern DSP parts we have. These clocks need to be synchronous or the part will just say "Hey!, Something is not right!" and mute! what it does is count transitions. 
 
 So assumptions I am making from your post. 
 Sampling rate is exactly 8kHz 
 Date size 16 bits and you have either a stereo signal or two channels. 
 With a 512kHz bit clock, this means that the bit clock is 64 x fs. 
 So this means you have 32 bits per channel and two channels. This is all fine. The data will either be left justified or delayed by one BCLK but either way as long as the setting matches what the modem is sending you are fine. 
 
 Now moving on to the more important details. The MCLK. 
 If you are sending an 8MHZ MCLK and an 8KHz LRCLK then the ratio of MCLK is LRCLK x 1000. 
 This will not work. The ratio must be fs x 1024. 
 So this means the clock feeding the PLL needs to be exactly 8,192,000Hz. 
 It also needs to come from the same source as the 8kHz sample rate so it always tracks the sample rate by 1024. 
 Then the PLL would need to be set to 1024, it is set to this automatically when it is enabled. You have to direct clock the part to have another ratio. But, it would still need to be synchronous. 
 This is from the datasheet: 
 The PLL output clock rate is always 1024 &times; fS 
 
 You are doing good to start simple, feed a signal into the ADCs and then look for SDATA out of the serial output port 
 You mentioned bypassing the serial ports using the mixers but this usually still involves the converters which will be muted if the clocks do not divide properly. 
 
 So let's start here and then move on if the clocks are right. 
 
 Thanks, 
 Dave T)

DaveThib · Answer

Hello Konradb, 
 You are correct that just getting an 8.192MHz clock is not the answer if it is not synchronous. You could add a PLL to bring up the 8kHz up to the 8.192MHz but that is not a cost effective solution. I would look into the ADAU1372 codec because it has sample rate converters on the serial input and output ports so the incoming master clock can be asynchronous and can even run on its own crystal. 
 Regarding the 512kHz clock for the bit clock. Standard I2S is a 32 bit data slot width for each channel and it is a stereo format. So the bit clock needs to be the FS x 64 which is what you have out of the modem. This is good and not a problem. 
 Regarding your question about the MAX9867, I think this part would also be good. I do not know this part very well so I do not know if there are other limitations. What are your available voltages in your system? Is it s 3.3V or a 1.8V system? 
 I will shout out to Mike who will know more about this part to see what he might have to add to this discussion. 
 MikeNunnery 
 Thanks, 
 
 Dave T

EdSellers · Answer

The MAX9867 does not require synchronous clocks, but it does require an MCLK that is 10MHz-to-60MHz. Assuming that you have a clock available in that range, and the inputs/outputs meet your requirements, the MAX9867 might be the more suitable CODEC. 
 I would be able to support any questions you might have if you decided to use this solution, including register settings tailored to your application.

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No I2S output

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