ADAU1761 not working on the ADAA24XX-EV-B2BX Eval Board

Hello MarkG1,

You have to include the read/write bit too in calculating your address, so your address will be 0x72.

Also please include a comms check circuit like below.

Please try this and let us know. 

Regards,

Harish

Hi Harish.

I have changed the address to 0x72 like you suggested, there is still no input

When using the DC and readback, it only reads 0 when there is a 1 or another number in it, so comms is not working.

Any other suggestions?

Thanks,

Mark.

Hi Harish.

I actually created a new project with your suggestions. It works now.

I must have changed some settings in the previous project when trying to debug.

Thanks,

Mark

Hi Harish.

While the above recommendation works for theADAU1761. On the same Eval board there is an ADAU1452. There does not seem to be any communication with this device. I have tried all the SPI addresses. There is no readback from the DC constant, even though there is no error reported.

Is there any additional configuration required for this device?

Thanks,

mark.

Hello Mark,

Could you please send the link to the Eval board user guide/schematic?

Regards,

Harish

Hi Harish.

I only have a pdf of the schematic. Can I send you that?

Mark.

Hello Mark,

Yes, please attach that.

if possible, also attach your sigma studio project (remove if any proprietary info is there)

Regards,

Harish

Hi Harish

See attached

PDF

I_O_1.dspproj

Regards,

Mark.

Hello Mark,

We have noticed that your PLL registers need to be changed for it to work properly.

1) Since you are using 24.576MHz MCLK input, your PLL input clock divider must be set to 'divide by 8'.

2) Then PLL clock source register is not quite correctly named so I understand the confusion, it is NOT the source to the PLL but the source to DSP (DSP core clock). So, it must be set to 'PLL clock' instead of 'Direct from MCLK'.

You have to use PLL clock out to be your core clock, so that the core will run at its highest speed which is 294.912MHz.

If you set 'Direct from MCLK', what would happen is, your MCLK in will be your core clock, in your case it's 24.576MHz which is 12 times slower than the nominal core clock, then the other clock generator rates derived from this clock will also be very low, so it won't give you the nominal sample rates.

Please refer the below screenshot and try again.

Regards,

Harish

Hi Harish.

I have experimented with the clocks and it was originally set to PLL. The file I sent to you was changed. With the above settings and the default SPI address I still have no communications with the device. 

Do you have a verified file on your end you could share?

Regards,

Mark.