Unable to selfboot

Hello,

Please share your hardware schematics and SS project, we will have a look and get back to you.

Also make sure that your I2C EEPROM address is set to address 0x50 (7-bit).

Regards,

Harish

Hello Harish,

Thanks for your reply.

I uploaded my answer again, I've been sent a reminder "Your EngineerZone Inquiry is Awaiting Your Response" even when my reply was the last reply. Nevermind

Address is correct, 0xA0. Here is schematic and simple test project. Please note that Q302 is removed from PCB, it was there to disable selfboot when USBi is plugged in.

Project here

6545.PassTrough.zip

Thanks

Best regards

Robert

Hello Robert,

Sorry for the delay in response.

Could you please try with ADAU1452 DLL (create a sigma studio project and drag and drop ADAU1452 IC and do the rest of the self-boot procedure).

I have an I2C EEPROM exactly same part that you have, but the I don't have the ADAU1450. But I have the ADAU1452, so when I tried with 1452, it works fine but with 1450 DLL it doesn't work for me. I will need to investigate further. I will keep you posted reg that.

The ADAU1450 is slower grade DSP, but Sigma studio clock settings are same as every fast grade project (PLL settings in GUI are same as 300MHz part. i.e default setting if you have 12.288MHz MCLK).  So, you can give it a try with ADAU1452.

You are using 512K bit memory, please fill the memory size in the EEPROM property window as 5,24,288 bits.

Also, after you have written to the EEPROM, unplug the USBi from the board and then initiate self-boot.

Regards.

Harish

Hello Harish, it works. Changed to ADAU1452, that's all it needed.

Thank you very much

Regards

Robert

Hello Robert,

One important thing that I forgot to mention is the MIPS usage. The 300MHz part like ADAU1452 has 6144 instructions per sample period at 48kHz. But, the slower grade ADAU1450 (150MHz part) only has 3072 instructions per sample period at 48KHz.

Since you are now using 1452 DLL, the compiler output calculates 100% resource with respect to 6144 instructions at 48kHz. But 1450 DSPs have only half of them.

So, if you are using the 1452 DLL, then you shouldn't use more that 50% of the resources. Watch the compiler window and DON'T exceed 50% of the MIPS usage. 

Compare the MIPS and memories like DM, PM between 1452 and 1450 and set the limit for 1450 and don't exceed that.

Additional info: Regarding the slower grade SigmaDSP part's core clock.

The ADAU1450 is slower grade SigmaDSP processors whose Core clock can go up to 147.456MHz. So, at 48KHz sample rate, you will get 3072 instructions per sample period (147.456MHz/48KHz = 3072)

whereas the faster grade SigmaDSP's core clock can be up to 294.912MHz and so, you will get 6144 instructions per sample period at 48KHz sample rate.

Coming to the GUI PLL clock settings between the slower and fast grade DSPs.

For slower grade DSPs, most people will try to scale the PLL clocks to match the slower grade clocks, but the thing is you don't need to do anything.

So, for the parts that run at the slower rate you will still setup the PLL for the faster rate, the rest will all be handled automatically.

The 1450 will have the same exact PLL and clock generator settings as the faster grade DSP.

The PLL is setup to operate in a fairly narrow range. The PLL for all variants will be in the region of 294.912MHz. Then there is a divider (internal) on the PLL output for the variants that operate at ~150MHz. The internal logic takes care of all the proper scaling of all the sub-systems that rely on the system clock. So, for instance, the clock generators will divide the system clock by 1024 (for faster grade DSPs). When the divider (internally present on slower grade DSPs) is active the pre-divider for the clock generators will be 512. 

So, you will end up getting same sub system clocks.

Below is a small representation.

after a feedback divider, your core clock will typically be 294.912MHz,

For faster grade DSPs,

This 294.912MHz clock will be divided by 1024 (pre-divider for CGs), so 294.912MHz/1024 = 288000Hz

Input to CGs will be 288000Hz, 

when scaling with CG1's N/M values, it will be 288000 x 1/6 = 48KHz.

In a fresh project (default config), this CG1 will drive the Sport (if master) and DSP sample rate (start pulse setting). So, the default sample rate in a fresh project is 48KHz.

(CG - clock generator)

For slower grade DSPs,

This 294.912MHz clock will be divided internally by 2 and will become 147.456MHz. When this internal divider is active, then pre-divider for the CGs will become 512.

147.456MHz/512 = 288000Hz.

Input to CGs will be 288000Hz (same value as faster grade DSPs)

when scaling with CG1's N/M values, it will be 288000 x 1/6 = 48KHz.

so, the CGs will produce the same clocks as the faster grade DSPs.

So, no addition PLL setting is required for slower grade DSPs, the PLL setting in GUI is just same as the fast grade DSPs.

For setting a 48KHz DSP sample rate from a 12.288MHz MCLK, below is the clock setting for both slower and faster grade DSPs.

(below attached screenshot is nothing but a default settings of a freshly opened project)

But, for slower grade DSPs, it is very significant to note that, the core clock going into the slower grade DSPs is just 147.456MHz, which is the clock used for executing instructions. so, you only have half the instructions available compared to faster grade DSPs.

at 48KHz, you will only have 3072 (147.456MHz/48KHz) instructions available.

if you are using faster grade DLL (software) like ADAU1451/1452 in GUI with a slower grade DSP (hardware), make sure that you don't exceed 50% of the MIPS (shown in the compiler output window)

Regards,

Harish

Harish,

Thanks for very detailed explanation. When I designed this prototype I haven't notice that 1450 is slower, now I see that I already exceed 50% of the MIPS. This was first prototype, because of some mistakes in PCB layout I have to go for second prototype anyway, it will use 1452 so I don't need to worry about MIPS.

Thanks & Regards

Robert