Hi,
I'm trying to cross-check the timings of various high-speed signals (SPI and audio TDM) between chips that are interfaced on our board, specifically the ADAU146x, AD2428, and our host SoC (TI AM3358), and I'm running into the issue that some of the timings in the ADAU1462 datasheet don't really make sense to me.
The biggest problem is that unexpectedly high values are specified for max data output delay from clock input, for both SPI:
and audio serial ports:
Contrary to the assurance given in the commentary, an output delay in excess of 20 ns (let alone 35) would preclude communication at the highest supported data rate (BCLK = 24.576 MHz) regardless of signal integrity, and it can't really be more than 10-15 ns to have a realistic expectation of being able to achieve reliable communication at that data rate in practice. In reality it does work just fine and we've measured the output delay to be about 5ns, nowhere near the datasheet value.
Similarly, if that 39 ns output delay for SPI MOSI were true you'd need to limit the SPI clock frequency to 8-12 MHz or so (depending on the host's setup time requirements), far less than the 20 MHz specified to be supported. In reality we've been running it at 16 MHz without problems in another product of ours and on the scope we see a mere 7-8ns output delay, which is indeed fine for 20 MHz.
Are these just erroneous values, or am I missing something here?
This isn't the only problem with the audio serial port timing specs of the ADAU1462, for example this setup time would in practice also prevent operation with a 24.576 MHz BCLK:
and I don't understand why it's given at a particular LRCLK frequency, it makes no sense for this setup time to depend on that.
Also, I have no idea what this is even trying to spec:
and more generally the collection of data-vs-clock timings are confusing and appear to be incomplete. I think it would help to properly separate timing requirements on inputs versus switching characteristics of outputs, and to cover all configuration options would require specifying at least:
- timing requirements:
- BCLK_INz/BCLK_OUTz input low time (min) and high time (min). Typically this doesn't depend on BCLK frequency/period.
- SDATA_INx and LRCLK_INy input setup time (min) to, and hold time (max) from, BCLK_INx output sample-edge (typ rising edge)
- SDATA_INx and LRCLK_INy input setup time (min) to, and hold time (max) from, BCLK_INz input sample-edge (typ rising edge)
- LRCLK_OUTy input setup time (min) to, and hold time (max) from, BCLK_OUTx output sample-edge (typ rising edge)
- LRCLK_OUTy input setup time (min) to, and hold time (max) from, BCLK_OUTz input sample-edge (typ rising edge)
- switching characteristics:
- BCLK_INx/BCLK_OUTx output duty cycle (min, max), e.g. specified as 0.5 tBCLK ± some amount of ns. Beware of jitter from clkgen when configured as fractional divider.
- LRCLK_INx output hold time (min) and delay (max) from BCLK_INx output drive-edge (typ falling edge)
- LRCLK_INx output hold time (min) and delay (max) from BCLK_INz input drive-edge (typ falling edge)
- SDATA_OUTx and LRCLK_OUTx output hold time (min) and delay (max) from BCLK_OUTx output drive-edge (typ falling edge)
- SDATA_OUTx and LRCLK_OUTx output hold time (min) and delay (max) from BCLK_OUTz input drive-edge (typ falling edge)
Here for clarity I've used x = port number, y = LRCLK_IN/OUT pin (if used as input), z = BCLK_IN/OUT pin (if used as input).
The timing diagram also has issues, e.g. tSODS and tSODM are output delay times but in the diagram they're being drawn as input setup times.
trivial typo fix
[edited by: matthijs at 10:22 AM (GMT -5) on 16 Dec 2024]