ADAU1452/1466 - Bypass, Decoupling, PLL and reservoirs

Hello Daniel,

You have a ton of questions. I will do my best to get through them. 

First, yes, the stray cap on the right side of the 1466 datasheet layout example is an error in the datasheet. 

Before I get too far I also need to mention that you will want to refer to the ADAU1452 RevD datasheet for the common elements between the ADAU1452 and ADAU1467 family of parts. I had put in a lot of work to update that datasheet back in 2018 and a lot of it was with the voltage regulator for the DVDD when I worked with the designer of the regulator before he retired to come up with the changes. It was a situation where the electronics industry has improved?...Changed?.. whatever you want to call it people are not using 10uf electrolytic capacitors as often since ceramic ones are now available at a reasonable cost but were not when this part was first designed. 

The other detail is that these PCBs were not designed by me. I was a little involved with the RevB board but not a lot. 

I was consulted when the codec did not meet specifications and I advised on the layout of the codec and that fixed the codec performance issue but I was not consulted on the DSP part of the layout. The investigations I did with the voltage regulator all happened after all the eval boards had been designed. So I really do not have a good layout to point to for you to copy. I wish I did. By the way, This is the post and the document I wrote up about the codec PCB layout: (+) PCB Layout Best Practices for AD193x codecs - Q&A - Audio - EngineerZone

The concepts are the same for the DSP.

 Question 1:

Yes. move these vias. 

You are correct, do not put the ground vias right by the pin. Make the trace to the pin go past a bypass cap before going to the via to the ground plane,

For your question 2 I will expand on a few things. 

I am glad you found the detail about the ceramic 10of caps and adding the 0.5ohm resistor. There is no real advantage to using the electrolytics. I think going to the ceramic caps is probably better because they do not dry out over time and change value! The only issue is that the regulator was designed with electrolytic caps in mind and the ESR of the cap is a real factor in the phase margin of the regulator. That is why you need to add the resistor in series with the ceramic cap. 

Notice that the ADAU1452 newer datasheet does not have the 1uf caps. This is because in simulation this reduced the phase margin. Do not use the 1uf caps and certainly do not add more than one 10uf cap. Having several 10uf caps will reduce the phase margin. The 10uf cap is for larger and longer lasting current demands so the placement is not as critical because there will not be as much of a high frequency "edge" to the demand so the inductance of the vias do not make a difference. The 100nf caps are the ones that handle keeping the short high frequency clock and data edges from becoming a problem. The caps work both ways, they keep the noise generated internally in the part from going out onto the power and ground planes and it also reduces any noise that happens to be on the power and ground planes from getting into the part. I would follow these bypass cap and via placement everywhere in your design. 

I do want to add one thing here. There is no such thing as a perfect PCB layout! You always have to make compromises somewhere in the design. I feel that understanding that you are making a compromise will help you minimize the bad effects and be on the lookout for issues once the PCB in in hand and being tested. As you have noted, our PCBs are certainly not perfect yet they work decently well. 

One other detail. When I was doing this analysis work I went into the lab and TRIED to make the regulator unstable by adding a lot of extra capacitance, and I mean a lot, and I was never able to get it to be unstable. So the design is good and the simulations are all over silicon variations and temperature ranges so my one nominal board at room temperature would not go unstable and oscillate. But, I went with the simulations since I did not have months to experiment with silicon skews and various temperatures. 

Question 3,

I think your PLL loop filter placement should be fine. I do not see anything that really stood out to me. 

Question 4.

Let's have a bit of fun here today,...What do you mean 0402 resistors are not replaceable by hand? About a two years ago I had to replace some sitting on my knees behind an audio console with poor light and only a large SMT tweezer and standard soldering iron tips! I got it done! But,... it was not pretty! We do this in the lab here at ADI a lot but we have small tweezers and a microscope!!  Even then it is still tough. So I get it! with my personal designs I do for "fun" I do not even use 0603, All of my resistors are 0805 so they are replaceable by mere mortals! 

That said, you really do need to use 0402 because you want to minimize the trace lengths and few turns and curves. Yes, these resistors are a great idea and I would for sure add them. They are best placed near the source but this can be one of those trade-offs I mentioned. It is better to have a more direct and shorter signal path than to have the resistor close to the source. Try your best to do it and it looks like you did a great job. 

Regarding on the SPI lines. That is a tougher question. If you are going to try to run as fast as possible with the SPI then yes, add the resistors. For our eval boards we only boot up from it and usually we use 10MHz at the most so the damping resistors are not as critical to be there. If you are going to use a RAM chip to do external delay lines then you will have to push the speed so then damping resistors will be important. You will be increasing the drive strength of the output pins which will make the transmission line ring more.  

So if you only have an EEPROM for booting up the DSP and you do not need to boot up as fast as possible then do not worry about the damping resistors. 

Well, This is my book for the day. LOL 

Sorry this was a little long. I obviously like talking about this stuff too much!

Dave T

Hey David,

Yes I am sorry for the long list of questions.. Im totally new to all this stuff and just trying to understand as best as I can. I really appreciate you taking your time to write such an extensive answer covering all my points!

Thanks for the tip on the datasheet. I didn't considder looking at the revision table of the two.. I will refer primarily to the 1452 then.

Im also happy that you say the Eval board isn't the ideal design. That took a lot of confusion off my shoulders! Especially compared with you good examples in the link you provided. Thanks!


So to summarize, just to make sure I got everything right:

1. Remove the 1uF caps on all the power pins and only use 100nF with the addition of 10nf on all the DVDD pins.
2. Only add one 10uf ceramic capacitor to each named rail. no more, no less.
3. It is okay to decouple the PLL supply (PVDDD) and the AVDD with ferite beads as shown? - I have seen this done on another DSP design using the 1452.
4. I2S resistor placement is okay - and no, mortals cannot desolder 0402 resistors, only gurus ;)
5. The resistors on the EEPROM lines are meaningless for boot up only, but do no harm?

This is the updated layout with now only one 10uF at each rail and no 1uF caps. Also I added some more vias and pours around the ferite beads and DVDD regulator. Does these make any sense or should I stay with a single via everywhere?

I also removed the trace (now dodded blue line) from connecting a IOVDD pad to the 3.3v input of the regulator. This is shown in the datasheet, but am I right that it doesn't mean it actiually needs a trace but just needs to connect to the same net?

Also the extra 10uF cap shown at the regulator for the DVDD net. I suppose this is not the required bulk capacitor needed at the chip? meaning there are actually supposed to be two 10uf caps on the DVDD net as in my current layout. Or am I wong? I chose to place the other 10uF as far away from the regulator one to sperad out the supplies.

FIY. this is the power plane on layer 3 (Layer 2 is pure GND).

Again, thakyou very much for taking your time answering all these noob questions! I don't mind it beeing long, share all you are willing to share! I'm a dry sponge at the moment :D

Best regards, Daniel

Hello Daniel,

DannerD3H said:

So to summarize, just to make sure I got everything right:

1. Remove the 1uF caps on all the power pins and only use 100nF with the addition of 10nf on all the DVDD pins.
2. Only add one 10uf ceramic capacitor to each named rail. no more, no less.
3. It is okay to decouple the PLL supply (PVDDD) and the AVDD with ferite beads as shown? - I have seen this done on another DSP design using the 1452.
4. I2S resistor placement is okay - and no, mortals cannot desolder 0402 resistors, only gurus ;)
5. The resistors on the EEPROM lines are meaningless for boot up only, but do no harm?

1) Yes, remove the 1uf. The 10nf are your choice. Not a big difference with them in or out when it comes to phase margin and I could only see a slight difference with the noise waveform on the pin when I did these tests in the lab. 

2) Yes.

3) Yes, ferrite beads are OK as long as there are bypass caps on both sides and usually there are. 

4) Give yourself some credit, some good equipment and a decade or two more experience and you will have it mastered!

5) The resistors are a good idea but usually not needed unless you are pushing the speed of the EEPROM up towards the max. So basically, yes, they do no harm.

Now I am going to start getting more picky. The ground fill on the top layer should not be allowed to touch a pin or a pad unless there is a via right there to the ground plane. Here is an example. Stop (block) the fill from getting to these pads:

Next:

A few comments about this area:

See where I added the red scribble? Get rid of the ground fill there.  But there is more... New screenshot:

Even though this is the 10uf cap, I would do this since it is easy to move the vias to the other side.

Next:

On this next place I would remove the ground fill where I noted and move one via to sit closer to the two bypass caps.

Next:

This next set of comments are not super important. Just minor details. 

I do not like to see any pins tied to the EP that is under the part. I feel it is best to let that get its ground from all the vias and not tie any of the pins to it. I have seen an issue when someone had tied the PGND and the DGND both to the ground fill on the top of the board and that caused a feedback path between the digital and analog sections of the part and caused the PLL to lose lock! In your case it is not as bad, and not super significant. Here is what I see:

The pin that is tied where I drew a red "X" is a stray DGND pin that is not closely associated with a power pin. However, it will still be tied internally to all the other DGND pins so I would not want to have stray currents or noise from the EP to get into the ground ring in the part. So if it is possible I would give it its own via to ground. 

The red circle are two logic pins that are tied to ground via the EP. These are the address pins for the comms port so there will not be a lot of current and not much of a chance to have any parasitic currents cause problems. So I do not have a great argument to say not to tie it there. 

Thanks for interest in these parts. They are a lot of fun to work with!

Dave T

Hello again David, Once again thankyou for a brilliant answer!

1. Gotcha!
2. OK
3. When you say bypass capacitors on both sides, I dont have anything directly on the outside. I just go straight down to the 3.3V power plane. Or do you then mean the 10uf cap on that plane is enough?
   
   Would it be better to use a seperate LDO for each of these rails instead of the Ferite bead? or is that nogo?
4. Well, a decade or two will probably help yes :P
5. Ok, I will just leave them in then.

I am glad you are getting picky, I feel like thats the real gold

I get the first three pictures, but the forth one I'm abit unsure why you only want to remove one of the ground fill connections. Is this also ok?

Thanks for the last comments as well. I think I got it all sorted out:

I also really like these DSP chips! A real shame I cannot use sigma studio commercially.. I wish I could program my Fusion amps with sigma studio xD

Bonus question:
All these details regarding decoupling caps and so on. Do they really have a meaningfull diefference, or only something detectable with a scope at the right prope point?
I ask because when looking at commercial products such as this one (I know its a SHARC processor, but not the only one where I have seen it)
Its pretty obvious that anything called bypass/decoupling is just tossed to the other side of the PCB.

Backside

Front
Pictures from this thread: https://www.audiosciencereview.com/forum/index.php?threads/minidsp-2x4-hd-ddrc-24-v2-simple-measurement-and-teardown-pictures.50900/

Hey Dave, happy new year!!

Did you have a chance to look at my last question? 

Hello Danner,

Sorry, I have been very busy and distracted. 

The item #3. Where I said caps on both sides of the ferrite bead. I was talking schematic wise not PCB sides. 

Here is an example but not a great one. There are caps on both sides of the ferrite bead. 

As far as the ground fill part of this discussion. Yes, I think you understood and did it right. It looks good. From the pin of the part you pass a bypass cap then hit the via to the plane then it gets to the fill on the top for the ground pins. 

Some people do use SigmaStudio in somewhat of a commercial way. But, it is mostly companies who sell kits and small audio devices that are meant for hobbyists and they just show them a link to our web site and tell people to download SigmaStudio if they want to customize the product and they include the default schematic. It can turn into a hassle for us because you get a lot of people who are not electrical engineers trying to figure it out. 

Most customers will program their own application that controls the DSP. One company actually has many different options for speakers, speaker drivers and crossovers and the installer chooses what is used and then their software will customize the EEPROM image. They are VERY much power users and were very good DSP engineers but still I had to help them a fair amount. They do super high-end home theaters and other film previewing rooms for Hollywood producers etc. Their audio performance standards are very high and they have been very happy with the SigmaDSPs. 

On to your last bit of comments. The placement of the caps and the little things I have been talking about, like the placement of the caps and the vias, is a bit of an art and also a LOT of engineers are not aware of the issues. I have studied signal integrity theory but many others have not. Also, the SHARC folks have very few parts that have legs. Most of their parts are BGA style of packages and in that case it can be super difficult or impossible to follow these recommendations. It comes down to how the designers layout the pins. When we merged with Maxim we gained a bunch of new engineers and I have been impressed with them. Their BGA footprints almost always have the power and ground balls around the edges or where you can run them together and go out the side of the part. Then you can place the caps on the same side of the board.  Some ground pins are only for references and not high currents so those are not as important. 

What I have found is that often these details will make no difference until they do. Kind of like balancing something over the edge of a table. It will not fall off. Keep moving it out over the edge and it does not fall. Then once you pass the center of gravity BOOM! it makes a difference. The last move was small but made a big difference. I feel these PCB layout things are similar. They make little to no difference until you reach a tipping point and then it is a problem. Many of our eval board are not done well in my opinion but many were done before I joined ADI. Then there is the thing I mentioned which is trade-offs. You can never design a "perfect" eval board. You will have to compromise somewhere and hopefully it does not cause you problems later. 

I have had several large automotive customers, well, the contractor who is doing the designs for the auto company, ran into issues with the amplifiers. They contact us and blame our chip. I come back and tell them the layout is the problem. After a lot of back and forth they make the changes and it solves the problem. So I have seen it make a difference and there are plenty of examples where it is not done well and the performance is fine! I think Mr Murphy may be involved in this and some Karma... So getting right with the spirit world will help as well! LOL.

I plan to make a video on this topic for my YouTube channel eventually. I have some ideas for demonstrations. 

By the way, in the signal integrity classes it was all about the return current paths. The parasitic currents. Where do they go? This thinking helps a lot for layout of things like clock lines and data lines. That along with good bypassing will keep the power and ground planes much more quiet. It certainly is an art and I "visualize" a lot of this. 

Dave T

Hello Dave, I can imagine, but thanks for getting back anyway! Your comments have been a great help and I think I might be ready to try and get my board made. It's mostly just a test platform for future projects and an attempt to learn PCB design. Whenever I get this working with an input and output board I will start combining it all in one PCB for specific projects. This was just an attempt to experiment with individual parts without having to respin everything every time.. Hope it was a good decision :)
 

Okay I think the ferite beads should be okay then. What do you think of the other approach of having a seperate smaller LDO's for each named rail (IOVDD, AVDD and so on)? Bad, Better?

Well... Im one of those people.. It all started with a Wondom DSP board which does just that, links to you and now I'm here.. I'm no electrical engineer, I'm a mechanical engineer.. So Sorry about that But thanks for the example. Sounds like a great concpt they have!

Okay.. From mechanical engineering I'm used to a more black and white theory than this, but at least it explains why it is a topic with som many contradicting and confusing guides out there.. Thanks for clearing it up! Gotta be nice to Murphy and get some good karma built up then xD

Will be looking out for that video!

I have read a lot about the return currents of DC vs high speed digital and think I understand the concepts, it was mostly this decoupling stuff along with misleading information in the datasheets that I couldn't get my head around..
All that said.. I do think there is at least a 50% chance that this board may go smoking on the first power on xD

Thanks for your help!
Daniel

Hello Daniel,

Well, keep up the good work! You are a perfect example of why I treat all the people posting seriously because you never know where they will end up. You are learning a lot and it is only a matter of time before you are working for a company that will design and sell a high volume of units! Figuring out datasheets is another skill for sure! I have written quite a few now and see how it is done and it is difficult to include all the info and not leave anything out and add all the measurement conditions. It is almost an impossible task. Then add to it the pressures of release schedules and editors! 

DannerD3H said:

I do think there is at least a 50% chance that this board may go smoking on the first power on xD

Gee, I have never had a board smoke or not work at first power up ... LOL, it is a rite of passage. If you have not done that you have not designed any boards. It is easier these days with all the design verifications you can do with the software but I still have had errors creep in despite all that! So cross your fingers and do not give yourself a hard time if there is a problem. Your board looks really nice. 

You can probably tell I am also a professor so I am used to helping students gain confidence!

Dave T

Hi Dave,

Great discussion, but I have a question. You wrote:

> I do not like to see any pins tied to the EP that is under the part.

That's a new one to me for when the EP is stated as GND in the datasheet versus just an isolated slug.

Given on the PCB there's a piece of plane (so low R, low L) and has lots of vias to the ground plane (again low R and L since the vias are in parallel) connecting a pin to that on the PCB vs breaking the pin out with a piece of trace that's going to a single via - I would go for the thing with the lower R and L.

I assumed when the 1452 datasheet says the EP must be grounded it meant it's also connected internally to GND (some special bond wires or something?).  But you're implying the EP is actually just floating?  But if it's floating then there's no current and therefor no noise from it?

If it's electrically connected to the substrate with conductive adhesive there still shouldn't be any appreciable current under normal operating conditions?  Going the other way, would current from a DGND pin that went to a via on the EP plane make that point noisier than the ground plane would already be if the GND pin was tied to a via connected to the GND plane few mm away?

1452 isn't really drawing gobs of power and/or seeing large, fast current swings when running, i.e. a few hundred mA at most?  If this was some 10W+ FPGA or CPU that's drawing a couple of amps at a few GHz, then yeah, be very careful.  But here, seems like a reasonably forgiving use case?

Please advise oh wise one :-)

Thanks,

Brewster

PS: Daniel, I have way more grey hair than Dave and I'm still learning...

Thanks for the confidence Dave ;)

I will let you know if it works or smokes! Will hopefully get it in end janurary :)


Brewster, if you stop learning then you must be bored :P

Hello Brewster.

This is best drawn out but I will try to explain it. Your analysis is spot on and correct. You mentioned that the PCB plane that the slug would be a soldered to it a good low impedance and low inductance path. Yes, indeed but here is what I have encountered and caused a serious issue with an automotive amp. 

The analog and digital pins on a codec were connected to the EP and lots of vias (7 or so) to the ground plane. the pins were tied to the "EP" plane and also had some traces away from the part and eventually to other places on the top ground plane and other vias. But they were further away. 

So the digital noise generated inside the part, (HF signals from the clock edges) would have a path to ground but the vias are inductive so there would be a voltage drop. This made this small plane ring with noise. It just happened that the analog sections of the part saw this path to ground as the lowest impedance and shared it. So now the analog section was picking up this digital noise. Well, the analog section of the part included the PLL so it would cause the PLL to lose lock or just not achieve a full lock. This small plane turned into its own small ground plane and a radiator and a shorter path than going to the actual plane. 

Since the bypass caps were on the other side of the pins they might have well just not be there. They were not effective. So the idea is to force the current to both the power and ground planes to pass by the bypass caps on the way to the plane. This will make them the most effective and keep noise from getting onto the plane and keep any noise on the plane from getting into the part. 

By the way, the troubleshooting of this issue all started because the TDM signal from the SHARC would jump from one BCLK delay to two BCLK delays! Intermittently! After a lot of work we found the PLL was not fully locked. So we switched focus and ruled out all the power supplies and other processors and anything else on the board. 

Then we asked the company for a PDF of the PCB layout and it jumped out at me right away that they had the bypass caps on the bottom of the board and this small plane on the top. This codec did not have an EP. 

So I asked them for a blank PCB. I soldered on just the codec and the bypass caps and applied external power and the PLL would not fully lock! They made my recommended changes to the PCB and they sent me a new one and Poof! locks quickly every time!

So the idea is to not have a shorter ground path between pins than if it were to go to the power plane. I suppose a small part with only one ground pin would not be an issue but those parts are rare. 

Dave T

Hello Brewster.

This is best drawn out but I will try to explain it. Your analysis is spot on and correct. You mentioned that the PCB plane that the slug would be a soldered to it a good low impedance and low inductance path. Yes, indeed but here is what I have encountered and caused a serious issue with an automotive amp. 

The analog and digital pins on a codec were connected to the EP and lots of vias (7 or so) to the ground plane. the pins were tied to the "EP" plane and also had some traces away from the part and eventually to other places on the top ground plane and other vias. But they were further away. 

So the digital noise generated inside the part, (HF signals from the clock edges) would have a path to ground but the vias are inductive so there would be a voltage drop. This made this small plane ring with noise. It just happened that the analog sections of the part saw this path to ground as the lowest impedance and shared it. So now the analog section was picking up this digital noise. Well, the analog section of the part included the PLL so it would cause the PLL to lose lock or just not achieve a full lock. This small plane turned into its own small ground plane and a radiator and a shorter path than going to the actual plane. 

Since the bypass caps were on the other side of the pins they might have well just not be there. They were not effective. So the idea is to force the current to both the power and ground planes to pass by the bypass caps on the way to the plane. This will make them the most effective and keep noise from getting onto the plane and keep any noise on the plane from getting into the part. 

By the way, the troubleshooting of this issue all started because the TDM signal from the SHARC would jump from one BCLK delay to two BCLK delays! Intermittently! After a lot of work we found the PLL was not fully locked. So we switched focus and ruled out all the power supplies and other processors and anything else on the board. 

Then we asked the company for a PDF of the PCB layout and it jumped out at me right away that they had the bypass caps on the bottom of the board and this small plane on the top. This codec did not have an EP. 

So I asked them for a blank PCB. I soldered on just the codec and the bypass caps and applied external power and the PLL would not fully lock! They made my recommended changes to the PCB and they sent me a new one and Poof! locks quickly every time!

So the idea is to not have a shorter ground path between pins than if it were to go to the power plane. I suppose a small part with only one ground pin would not be an issue but those parts are rare. 

Dave T

Hi Dave,

Thanks for the explanation. I can believe that, though part of me is thinking there was something else going on in that specific case.  But can't argue with success...and I have battle scars from long ago trying to make stable low jitter PLLs out of discrete parts.  One must invoke the dark arts sometimes :-)

One last question so I'm clear on it: The ADAU1452 PLL section ground is not tied to chip's DGND?  Wouldn't that make a rather large loop for the return currents from the PLL output?  Granted on chip it's like an very tiny current, but the electrons gotta go somewhere?

Brewster