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ADAU1452 at 96kHz into ADAU1787 at 768kHz via I2S

Category: Software
Product Number: ADAU1787

Hi All,

I am working on a project where I need to run a ADAU1452 with external ADC's and DAC's at 96kHz samplerate. The ADAU1787 get its signal from the ADAU1452 via I2S at 96kHz samplerate interpolated to 768kHz. 
The issue I'm having is that I can get signal into the ADAU1787 at 48kHz samplerate, but I cannot figure out how to get it working at 96kHz samplerate.
Before I dive back into the hardware I would like to check if there is anything I'm missing, as in this case there is lots to overlook.

Some facts/notes:

  • The ADAU1452 + ADC's + DAC's are all working fine at 96kHz samplerate. 
  • The ADAU1787 SDSP core sampling rate is not critical, either 48 or 96kHz will be fine.
  • The ADAU1787 FDSP core needs to run at 768kHz sampling rate. It's ADC's and DAC's run at the same rate.
  • The two IC's are running in one Sigmastudio project, both communicating over the same USBi via I2C.
  • The MCLK frequency is 24.576MHz.
  • It is preferred to have the signal enter the ADAU1787 via the SDSP core for additional processing and metering, but directly into the FDSP core via an interpolator is ok too.
  • There's a return signal from the ADAU1787 to the ADAU1452 that I'm having the same issue with, but that is not critical and I assume it is not working for the same reason.

The stripped project with just IO and notes is attached below. 

ADAU1452 + ADAU1787 I2S 96kHz.dspproj

  • Hello JRE,

    This will take a bit to dive into to see what might be going wrong. My first glance it looks like the 1452 is setup properly. I have to look closer at the 1787. That part I do not support as often so one of my colleagues may chime in or help me with that. 

    I have a question, are both the ADAU1452 and ADAU1787 running off the same master clock? I noticed you are not using the ASRC in the 1787 to take in the audio from the 1452 into the 1787. They would have to be on the same clock domain for that to be possible. Then you could run the 1787-SDSP at a 96kHz rate and not need to do any sample rate conversion. Then use the SRCs to go up to the 1787-FDSP rate from there. That signal flow will probably be the best. 

    At 48kHz you mentioned that you had it working. Did you have it round trip between the 1452 and the 1787? 

    You have the 1452 output serial ports set to be a master and that is good, it is the best for the clock direction to be the same as the data direction. This gives you the best timing margin. I have to think a little more about how to handle the data coming back. Are you using both serial ports on the 1787 or just one of them to send and receive? I can look at the project later but I want to be sure of your intentions and how you have the hardware connected? 

    Thanks for including the project. 

    Dave T

  • Hi Dave,

    Thank you for looking into my question and the quick response.

    Everything in the system is ran off of the same 24.576MHz master clock through a fanout buffer (NB3V8312CMNG), each IC on its own output..
    The ASRC is indeed not used because the signal flow that you are describing is what I am trying to achieve in the project.
    Just to be sure, do I understand correctly that with SRC you mean the interpolator between the SDSP and FDSP cores?
    This worked with everything set for 48kHz, including the return/round trip from the ADAU1787 back to the ADAU1452. 

    One note about the return signal that will probably be useful: this will transport back one of the ADAU1787 ADC's to the ADAU1452 through a decimator that outputs at 96kHz. No processing is required before entering the ADAU1452, so the decimator could directly output to the serial port, but I have it going through the SDSP in the project for metering/debugging etc.

    I am using seperate serial ports on the ADAU1787 to send and receive for more flexibility.

    Jeroen Roth

  • Hi Dave,

    After your reply I decided to look more into what IS working to see if that could give us some clues. Because of this I have already been able to find the solution.

    The I2S send and receive between the two IC's at 96kHz actually did work with the project as is. The meters were showing signal, but I had not given it enough thought. 
    At a given point I decided to remove all of the processing cells in the FDSP to see if signal would would pass, and it did. I then added the cells back in and started removing them until signal started passing to pinpoint the interfering processing cell. The issue is in a parametric EQ cell.

    What happened is that changing the project cell rate from 48kHz to 96kHz also changed the FDSP parametric EQ cell rate that should stay at 768kHz. 
    I was already running the FDSP at its limits with one very low frequency feedbackloop shaping filter, this specific filter stopped passing the audio with the new cell rate.
    Doubling the frequencies in the parametric EQ cell solved the issue and got the feedbackloop back to where it was.

    I kind of understand why it does this as there is no seperate FDSP cell rate setting, but it is not a very intuitive method. 

    Is there any documentation explaining this in more detail?

    Jeroen Roth

  • Hello Jeroen,

    Thanks for the report and taking the time to post it. I will report this to the programming team. Seems like you found a bug for sure. The propagate the sampling rate should not include the FDSP or should at least ask! It is going to be VERY rare that the FDSP core will be running at the same rate as the SDSP. 

    This is a growing pain kind of bug. The older parts either only had an SDSP or an FDSP not both. So the main program framework was not changed to deal with that. I can give the programmer a break that something like this is easy to miss. 

    Dave T