ADAU1466
Recommended for New Designs
The ADAU1462/ADAU1466 are automotive qualified audio processors that far exceed the digital signal processing capabilities of earlier SigmaDSP® devices...
Datasheet
ADAU1466 on Analog.com
Dear Team,
I am using Sigma Studio v4.5 and ADAU1466 Evaluation Board.
We have read the ASRC datasheet and from the datasheet it appears that the delay introduced by ASRC for 192Fs out 48 Fs In case is approximately 1ms.(refer below )
When we add a signal from ASRC (48 Fs upconverted to 192 Fs) and Serial Input (192 Fs) the output from ASRC seems delayed resulting in samples leftover from ASRC as shown in red circle in image below
Below is my query shown diagrammatically. Sample rate of the system is 192Fs. Could you please let me know this is expected to have samples from ASRC channel at the start or end when adding ASRC and Serial Input signal ?
Regards,
Zayn
Hello Zayn,
The latency I have measured has always been around 1ms so your calculations are correct.
I do want to comment on one of your settings. You have the ASRC Output Rate set to one of the serial output ports. I assume this is set to 192kHz but if you are going from a serial input port to the DSP core, then it is best to select the "DSP Rate" setting so it will follow the DSP start pulse register setting which is the exact sampling rate of the core. If the serial output port is set to an internal rate of 192kHz then it is technically the same clock so the setting is not wrong but might surprise you down the road should you change the serial port settings.
If you analyze what you are doing you will have your answer. you have two signals coming into the serial ports and again, I am assuming a few things since you did not include a project so I can look at other settings and also, the screen resolution of the inserted pictures is not good enough to actually read the settings.
I am assuming the serial input port 0 is set to 192kHz fs.
I am assuming serial port input port 1 is set to some other rate (48kHz is what you mentioned) which is why you need the ASRC.
The serial ports are objects that operate on their own. Serial port 0 will have the 192 clock so four new samples are deposited into a memory location for every one sample deposited into a memory location for serial input port 1. The clock edges I can assume to not be precisely lined up. If they are on different master clocks then these edges will drift around as the rates shift around. If they are on the same master clock then they will be locked but exactly where the edges are will change with every startup.
We have a resyncing clock cycle to decide whether to pass on the sample during this sample period or wait one sample period. If it comes a little late then it will have to wait. I do not have more information than that on how this works. This is the variable latency that cannot be avoided if the two sources are asynchronous. If they are synchronous then it may be more deterministic if the sending devices are more deterministic. Some of our codecs can be variable because of things like PLL lock times. The counters for the sample rate dividers do not start until the PLL is locked. You can get around that by direct clocking but this is another discussion.
your question hints about what happens at the start of stop of the ASRC. The ASRC memory will not be cleared so the first millisecond will have either random data or old data until it is flushed with new data. This is why I have some programs setup to mute the audio and have a ramp up of the audio allowing the memory to clear before it is audible.
So back to your question. The samples on serial port 0 will be available for the core to pick up right away. The serial port 1 will deliver its sample to the ASRC but the ASRC will take 1ms for this signal to get through the filter. You will not have the data available at the same time. The fix would be to delay the serial input port 0 audio by 1ms and then they should be better lined up. It is still difficult to know exactly the phase of the signal between the two will be because it will depend on when the samples are presented to the serial port and hence to the core. Not knowing your application I do not know what is significant for you.
Dave T
Dear Dave !
Thanks for your response .
Please find my reply inline below:
"I am assuming the serial input port 0 is set to 192kHz fs.
I am assuming serial port input port 1 is set to some other rate (48kHz is what you mentioned) which is why you need the ASRC."
Zayn: You are correct !
"The clock edges I can assume to not be precisely lined up. If they are on different master clocks then these edges will drift around as the rates shift around. If they are on the same master clock then they will be locked but exactly where the edges are will change with every startup. "
Zayn: Why should the clocks not be precisely lined up ? There is only one single clock provider and it is the ADAU1466 Master Board . The ADAU1466 Slave boards uses no clock of its own , infact all the four serial input and output ports are slave from their clock domains. As such shouldn't the clocks be aligned well. The only difference is i am providing TDM4 clock to Serial IN 0,2 and 3 and providing TDM 8 clock to Serial IN 1 . The Serial Output ports are also all slaves and I am providing them clocks from this very board.
Most importantly is there a way to prevent the edges from changing with every startup or LCD?????
"The samples on serial port 0 will be available for the core to pick up right away. The serial port 1 will deliver its sample to the ASRC but the ASRC will take 1ms for this signal to get through the filter. You will not have the data available at the same time. The fix would be to delay the serial input port 0 audio by 1ms and then they should be better lined up. "
Zayn : We will check on this fix of adding 1 ms delay to Serial input port 0 and revert back to you.