Hello,
I'm working on a project with double ADAU1467. The block diagram is the next:
I have ADC1 and ADC2 connected in TDM8 mode to DSP0_SDATA_IN0 (4 channels each ADC), ADC3 connected in TDM8 mode (only first 4 channels used) to DSP0_SDATA_IO0. Then the signals go to DSP1 (with TDM8 ports) and to the DAC (with TDM8 ports).
The signals from DSP0_SDATA_IN0 work well, but the signals from DSP0_SDATA_IO0 are not working, the sound is completely wrong.
All the BCLK and LRCLK are connected each other (ADC, DAC, DSP): the DSP1_OUT0 port is BLCK/LRCLK master (Drive Strength Highest) and all the other ports are slave (note that the two DSPs have the BLCK/LRCLK of IN0 and OUT0 port connected each other).
The MCLK for DSP1, ADCs and DAC is generated from DSP0.
I made some tests:
- I inverted the ADCs with the same result (so all the ADC are working well)
- I used a internal sine from DSP0 as audio sample and everything works well
- If i set MCLK_OUT on DSP0 to 12Mhz everything works fine, but I need 96kHz application, so the MCLK must be 24,576MHz
It seems that the problem is the SDAIO port. Do you have any other ideas? How should i configure the ports?
I attach the project.
Thanks
Marco Silenzi
