ADAU1467 PLL

Hello Sudhir,

There is some detail about this in the datasheet but it is a feature with limited usefulness. You will not be needing this feature and chances are you probably will not even be using Clock_Gen_3. 

I have a lot of questions if you do not mind answering then I can be of more help. 

What is your application?

What audio processing are you looking to do?

What hardware platform are you using? Is it our evaluation board or your own board? If it is ours then let me know which one. 

Are you planning on using A2B networks in your application? The reason why I ask is to see if you could use the older version of SigmaStudio or stay with SS+. 

For your application details, the clocking details are important. A clocking block diagram showing the main parts of the system to show where the clocks are coming from and to. Show which is the master and which is the slave.

What is the master clock frequency?

What is the serial format. You mentioned I2S so I guess that is it.

What sampling rate?

Dave T

Hi Dave thank you for reply.

1= my  application is  I'm building 8way stereo system with 8 amp each high, mid, mid low, and sub for each side. 

My last build was with ADAU1701. Audio source was I2S from ESP32 Bluetooth receiver on 44.1khz sampling rate. Bclk, LRclk, data, to ADAU1701. and master clock was 11.289Mhz from ESP32 was direct given to MCLKI pin 32 of ADAU1701. ''The serial data clocks need to be synchronous with the ADAU1701 master clock input''. not using any of ADC or DAC of ADAU1701 just digital in and digital out. and DAC I was using PCM5122 it doesn't need master clock. work with 3wier I2S.

2= audio processing ADAU1467 I'm using this time.

3= hardware I'm designing my own. in proses of designing PCB.

4=  planning for same application 8way stereo system with 8 amp. But more inputs and also want to use raspberry pi as audio source and raspberry pi I2S out put is only  "3wier I2S" no master clock. And want to use SPIDF in.

5= sampling rate depend on inputs from 44.1khz to 192 kHz.

ill explain about  hardware in some detail.

for master clock I'm using si5351-c (PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK GENERATOR) it can synchronous master clock with incoming master clock from input. plan is to read incoming sampling rate with microcontroller and set master clock as par. like if  incoming sampling rate is 44.1khz then set master clock for 11.289Mhz and if 48khz then set master clock for 12.288Mhz. 

and for eeprom I'm using M25PX80 NOR Serial Flash 8Mb.

for DAC I'm using AK4493 with I2S interphase.

 I'm little confuse about raspberry pi "3wier I2S" interphase. 

And purpose of this question about CLK_GEN3 was can I give incoming master clock like 12.288Mhz to one of MPins  in "FREF come from" setting so I can omit si5351-c proses. Is "FREF come from" setting for synchronous clocks. 

And can I switch multiple incoming inputs with MPins. 

Thank you once again.