8 channels with 16 BCLK per channel

Hello Eate77,

What I find strange is that the diagram you posted from how I read it shows a 32 bit wide slot.

This part does not have an exact register setting for a 16 bit wide slot but you could fool it by packing two 16 bit words together and treating it like TDM4.I could show you an example program if needed. You would just select four channels of 32 bits wide and pack in eight channels. 

Here is a project that shows how to pack and unpack but it is not setup for TDM-4 but that is not hard to change. 

Dave T

ADAU1452 16 bit Data Pack and unpack.dspproj

Hello Dave,

yes the diagram shows 32 bits (D31) but when handling 8 channels, it's only 16 bits per channel (which is in fact in contradiction with the digram)

thank you, the pack/unpack 16bit works perfectly

thanks to your support, i well progressed on my design.

Now i have some distorsion in my conference between serial port 3 in and out.

i attached an audio recording taken from the CH0-1 on the ADAU1467EVB

Do not pay attention to the noise in backgroung, its due to ground coupling between my radio and the computer

but in the middle of the record, you can hear some distorsion. I have this issue almost every 10 seconds.

Do you have any idea ?

This is my project : 

AVD1 CONF 6 channels (TDM4 32 bits).dspproj

Hello Eate77,

You need to document and draw out your system clocking details. This will show the issues. I see several things in your project that bring up red-flags to me. You are running the Serial input port 3 as a clock slave. So you are slaving to some external device, what clock domain is that device on? When I say "clock-domain" it mostly refers to the master clock. Is it on a different master clock or on the same clock that the DSP is using? 

Then the serial output port is operating as a clock master. Is this output port connecting to the same device? 

Then sampling rate is a big issue. You are running this output serial port at 16kHz fs. I have no idea what the actual clock rate in on the serial input port since it is a slave. However, the DSP core is operating at 48kHz fs. You also have SigmaStudio setup for 48kHz. The noise you demonstrated in the audio sounds a lot like it could be aliasing. With drifting clock rates it can come and go as the sample rates drift around relative to each other. 

I suggest you draw out a block diagram showing your system clocking. What is working on what master clock domain, what is a clock master, what is the format, what sampling rate. Etc. This part is super flexible with clocking so I am confident the system can be devised to work well. 

Also, do you have a system controller or will the DSP be running on its own?

I will be out of town for almost the next two weeks so my responses might be delayed.  I will try to check on EngineerZone but I will be relying on help from others. 

Thanks,

Dave T

Hello DaveThib 

thank you for your help.

this is the implementation : 

i've some doubt with the level shifter, as the max voltage for pulse below 1000ns do not reach 3.3V, despite the additionnal pull-up to reduce the Propagation delay time.

i'm tryning another level shifter (SN74AXC8T245)

Hello Eate77,

This helps although I still think you are leaving out some important information. In your project you are using two channels of the codec to probably monitor the signal. So you did not show the codec at all in this diagram. I made the assumption. 

Your diagram shows In3 as the master and out3 as the slave. Your project resister settings are the opposite but it really does not matter much since you have them tied together externally. Which is correct. 

I assume you are running the DSP at 48kHz because of the codec? You HAVE to use some ASRCs here. I would just run the entire DSP at 16kHz but if you want full bandwidth audio to the codec then it would make sense to use the ASRCs to go up and down to 16kHz and run the core and the codec at 48kHz. However, the problem lies with the ASRCs. They are only 24 bit and they do filtering to the audio of course. So you cannot send this packed 32 bit data which has two channels of 16 bit audio through the ASRC then on to the serial port. Or the other way around, come in and go to the ASRC then to the serial input port. This project might be able to be made much more complicated to go out to the ASRCs then back into the core then back out. It could be done but it is tricky. 

At the moment I setup your project to run the entire core at 16kHz fs and then just use the ASRC to go up to 48kHZ to send the audio to the DAC for monitoring purposes. 

This should take care of your strange noises. 

I know what you mean about the level shifters. I ran into issues with them years ago. The ones that sense the direction of the signal have really poor drive strength. So my suggestion is to choose ones that you have to set the direction with a pin. These are much better. 

The good news is that at 16kHz the timing is quite relaxed. 

Here is the project I edited.

Dave T

AVD1 CONF 6 channels (TDM4 32 bits)-DT-Edits.dspproj

Hello Dave,

i monitor the audio thanks to the CODEC integrated on the EVM.

to simplify my investiguation:

- i changed the Fs to 16Khz on each blocks

- i replaced my level shifter (directional one : SN74AXC8T245)

i still have the issue despite these changes but in a different manner depending on whether the ADAU is FSC/BCLK master or slave : 

First, let me describes the audio format coming from the component (DA14AVDDECT) interfaced to the ADAU :

the Frame Sync is 16Khz.

it's a TDM8 of 16 bits BUT ... on each frame, the number of Bit Clock is 144 (not 16 x 8 = 96)

Here is the different behaviour :

• WHen the ADAU OUT3 or IN3 provides the FSC/BCLK to the DA14AVDDECT:  the distorsion is present in the audio conference (IN3 to/from OUT3)za

• When the DA14AVDDECT provides to the ADAU (IN3 and OUT3) the FSC/BCLK :

the audio is good without distorsion but the audio conference doesn't work properly : the firsk pack of 16 bits of input40 do not carry my channel 1 (out of the 8 channels)

I can see activities (16 bits just after the FSC) with my oscilloscope but this stream do not enter in the DSP

The channel 2,3,4,5,6,7,8 are ok.

here is an export of PulsView of 6 channels, on this example, the 1st channel (channel 0) is not treated by the DSP.

here is my new design with the "Audio Signal Router" which is perfect for my expectations

SafeComm_Pro (with Audio_Router) V0.1.dspproj

Do you have any idea ?

Thank you for your support !

Hello,

here is some explanations from the support of the DA14AVDDECT: 

if the ADI DSP is in PCM slave mode it should start counting 8-channels x 16bits after the FSC pulse is received and then ignore the remaining 48 dummy bits.

Then repeat the sequence again after the next FSC pulse is received and so on.

 

Do you know if the ADI DSP support the TDM format send by the DA14AVDDECT? If so, is it setup correctly on the ADI DSP?

What I mean is that if the ADI DSP is aware that the FSC pulse is only 1 bitclock pulse wide?

For example (what might be happening), when the ADI DSP thinks that the FSC pulse is one channel wide (meaning 16-bits) and start counting after the FSC pulse is received, then it will skip the first channel.

What do you think about it?

Best regards,

Sebastien

Hello,

here is some explanations from the support of the DA14AVDDECT: 

if the ADI DSP is in PCM slave mode it should start counting 8-channels x 16bits after the FSC pulse is received and then ignore the remaining 48 dummy bits.

Then repeat the sequence again after the next FSC pulse is received and so on.

 

Do you know if the ADI DSP support the TDM format send by the DA14AVDDECT? If so, is it setup correctly on the ADI DSP?

What I mean is that if the ADI DSP is aware that the FSC pulse is only 1 bitclock pulse wide?

For example (what might be happening), when the ADI DSP thinks that the FSC pulse is one channel wide (meaning 16-bits) and start counting after the FSC pulse is received, then it will skip the first channel.

What do you think about it?

Best regards,

Sebastien

Any idea about my problem ?

Hello,

i still have my issue described above.

Let me explain it again : 

here is the different behaviour :

• WHen the ADAU provides clock to the DA14AVDDECT (SDATA_OUT3 : BCLK and LRCLK is master) :

i can hear some strange aterfact in the audio and so far i did not understand the reason.

• When the DA14AVDDECT provides clock to the ADAU (SDATA_OUT3 : BCLK and LRCLK is slave) :

the audio is good without distorsion but the 8 channels doesn't work properly : the firsk pack of 16 bits of input40 do not carry my channel 1 (out of the 8 channels)

I can see activities (16 bits just after the FSC) with my oscilloscope but this stream do not enter in the DSP

The channels 2,3,4,5,6,7,8 are ok.

here is an export of PulseView of 6 channels, on this example, the 1st channel (channel 0) is not treated by the DSP.

here is my new design with the "Audio Signal Router" which is perfect for my expectations

SafeComm_Pro (with Audio_Router) V0.1.dspproj

Do you have any idea ?

Hello Sebastien,

I have been working on this all day. This is not easy. 

This format is very strange. With 144 BCLK transitions per frame means that 144/8 is 18 bit clock transitions per channel slot. Then it is stuffed with 16 bit data. So every channel slot has two bits of zeros padding the data and you can see that in your data analyzer. 

We have what is called the flexible TDM mode which allows for unusual TDM data setups but it is limited. It groups the data into bytes and 18 bits does not divide by 8. So this means the data will need to be adjusted to be in the correct position and the sign extended. 

In my analysis it would need four different calculations to get the eight channels properly converted. 

Since it is that tricky I am leaning towards just brining the data in as 32 bit data and bit banging to split up the data. 

I have one question while I work on this. Are you using the delay by zero or delay by one setting in the format? It is shown as an option in one of your first pictures you posted. 

It makes a difference as to how I extract the data. 

Then I have one more detail that I asked for a long time ago and you did not provide with the clocking details. What is the master clock frequency? Who is providing it to the system? Is it going to both the ADC and the DSP?

I setup my Audio Precision to output this 144 bclk signal with 18 bit wide slots and 16 bits of data but the master clock ends up to not be an integer relationship to a 48kHz rate. I need to take the Flexible TDM output and send it to the core to properly extract the data which means I cannot send it to the ASRC. How are you dealing with this issue of the master clock? 

I am beginning to think you need to choose another part. We have plenty of codecs that would work very well. 

Thanks,

Dave T

Hello Dave,

many thanks for your support ! really appreciate.

DaveThib said:

So every channel slot has two bits of zeros padding the data

i'm not sure about that, Renesas says : 

The DA14AVDDECT is making a frame of 8x16bits with 48 dummy bits to make a bit-clock of 2.304MHz. This is a multiple of the bitrate in DECT (1.152MHz). 

If the ADI DSP is in PCM slave mode it should start counting 8-channels x 16bits after the FSC pulse is received and then ignore the remaining 48 dummy bits.

Then repeat the sequence again after the next FSC pulse is received and so on.

DaveThib said:

Are you using the delay by zero or delay by one setting in the format? It is shown as an option in one of your first pictures you posted. 

i'm using I2S - BCLK delay by one (but for your information, i have possibility to change this settings on the DA14AVDDECT 

DaveThib said:

What is the master clock frequency? Who is providing it to the system? Is it going to both the ADC and the DSP?

a 12.1288MHz oscillator provides the MCLK of the ADAU1467

the DA14AVDDECT has it own internal MCLK

DaveThib said:

I am beginning to think you need to choose another part. We have plenty of codecs that would work very well. 

really ?! unfortunately, we already release a prototype based on this couple. since it works when the DA14AVDDECT is master (except that in this scenario I lose the 1st channel).

Dave, would you be willing to participate to a call with Reneasas to discuss this topic ?

Hello Eate77,

There is something very wrong with the information I am getting from you verses the documentation from Renesas.

If there are 144 bit clock cycles in one frame and there are 8 channels then there are 18 bits per channel! Period end of sentence. There is NO WAY there can be 48 dummy bit clocks per frame with 8 channels of 16 bit data. 

16 x 8 = 128 bits

128 + 48 = 176 not the 144 you reported. Something is wrong. 

Your screenshots look like it could be only two bits but I cannot tell. Look at my old post on how to look at these signals on a scope and you can actually see each bit if you speed up the sweep.

(+) How to Take Meaningful Screenshots of I2S Audio Signals - Q&A - Audio - EngineerZone (analog.com)

I have been working on this all day Friday, I also worked on it some over the weekend and most of the day today and running into issues with trying to get this 18 bit channel slot size to work. I really have to move on to other issues that I have been putting off of some big customers. 

It is bad that each part is on its own MCLK domain. This will cause problems later depending on the solution. Because I have to use the core to do some bit-banging which means the data needs to be synchronous with the MCLK because I cannot go into the ASRC because it is not split up properly to do the math for filtering. 

So the issue is that you lose the first channel? if you slave to the incoming clocks? How are you getting the other channels with this format? There is some important information I am not getting here because things are not making sense. 

I wish you were nearby to be able to actually send the hardware to me. 

Maybe take some screenshots using a scope and give several. Some with the entire frame in view. Then a couple of channels and then just one channel zoomed way in so I can see the bit clocks. 

Also, the start of the frame zoomed in. 

A logic analyzer is not good for this. You cannot see the over and undershoot and the slope of the clock/data edges. 

Dave T

Hello Dave,

yes you're right, Renesas mentions about 144 bits and 48 dummy bits for 6 channels ( 16 x 6 = 96 bits -> 96 + 48 = 144 bits)

i saved many traces from my oscilloscope, i'm going to send them by email. you'll see 144 x BCLK with the dummy bits at the end (16 for 8 channels)

DaveThib said:

So the issue is that you lose the first channel? if you slave to the incoming clocks? How are you getting the other channels with this format? There is some important information I am not getting here because things are not making sense. 

Yes the 1st 16 bits available on SDATA_IN0 (channel 1) are totally ignored if the DA14AVDDECT provides BCLK/WCLK.

Yes, the next channels (channel 2 to channel 6) are perfectly managed by the DSP with the same settings

DaveThib said:

It is bad that each part is on its own MCLK domain.

the DA14AVDDECT does not have any input or output available for the MCLK. But normally Word Clock 

DaveThib said:

I wish you were nearby to be able to actually send the hardware to me. 

yes no problem, i can prepare one PCB.

Once again, thank you for your help