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PLL losing lock intermittantly

Category: Hardware
Product Number: adau1

PLL losing lock intermittently

I have a mature design with 8 x adau1701 in one PCB piece of insturmentation.   All APs are synced to one common MCLK clock running at 12.288 MHz (I think).  The design has been released for 3 years and we have produced approx 100pc without issue.  Most recently across a batch manufactured we have some APs are breaking out of lock unpredictably.

The condition is very very peculiar in my experience of PLLs.   The VCO in the chip is held (by the PLL loop) to within a few 100Hz of 12.288MHz * divider   (this is about 10-20ppm of locked)  by the PLL but drifts at a frequency every so slightly higher than reference.   If I slightly bias the PLL_FL pin (the VCO line I assume) with a resistor of 100K to 3v3 the device locks.  Biasing it high causes the osc to approach lock from the low F side.       I have tried many many combinations of loop filters and the only thing that seems to have any effect is the resistor.    Many APs will actually lock with no filter caps suggesting that the lock mechanism is normally robust.    Anything from 1M to 47K seems to help a lot.  <10Kohm knocks it out completely as I would expect.      My general experience is that PLLs will lock or jitter but I have never seen on run continuously out of F and phase BUT by such a TINY and fairly consistent amount (+20ppm)

The occurrence is intermittent and in some cases gets better after 10 mins or so running and in others only starts after 10 mins.    I have looked very closely at the loop filter pin and the MCLK signal. The MCLK it is right on 3V pk-pk with risetimes of about 5-10ns.  Looks v clean.   I can measure no difference in impedance between PLL_LP and adjacent components or rails on good and bad devices.   I am pretty frustrated by now and would appreciate any pointers at to root causing this issue.

about 5% of AP devices are affected.   Because my app requires synchronous behaviour between the APs I cannot live with this. 

I note from Ezone that there have been similar issues in the past that sound rather similar but were taken off line. 

HELP 

Dan Linehan

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  • Hello Dan,

    Sorry to hear about your issues. 

    We have sold many millions of these DSPs over a good 15 years or so and there has not been an issue with the recommended PLL loop filter components. You need to use the circuit shown in the datasheet with those values. 

    I would look to see if you are using quality capacitors for the loop filter. NP0/C0G are the best ones to use. PCB layout could also be an issue but since this design has been working for a while earlier I do not suspect that is the issue. 

    Are you using a crystal? I am wondering about the crystal itself. The drive strength of the crystal in this part is on the high side. That said, it sounds like you are distributing the MCLK so you would not have the crystal directly attached onto the part. By the way, most of the other reported issues that were taken offline ended up to be crystal issues usually. 

    The 3V MCLK level is a little low but it is well within the digital levels spec. It would be interesting to see the waveshape. Are there any reflections? Take a screenshot of the MCLKI pin. The shape of the waveform may enter into this problem. 

    Dave T

  • Dave

    Thanks for the fast reply. Will do photo later and will look extra closely at the MCLK signal. Yes, no Crystal. SIgnal is generated by uC and shared by all 8 APs parts. Any comment on the peculiar aspect of non-lock. Does this point you toward any likely mode or mechanism of disturbance. Any further details on how the PLL loop works. Is the freq/phase comparator a freq/quadrature type or simple mixer type. I suspect noise on a supply. Which of the chip supplies is the VCO run from / might I focus on.

    thanks

    Dan

  • you can see a video of the lock difference between two APs - one locked and the other not.   The carriers are 10kHz generated from each of the APs so the drift is v v small.   Will send pic of clock signal shortly.   I have to set up for it. https://photos.app.goo.gl/Lad18uRq4A1vgZeXA

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