ADAU1466 SPDIF INPUT to I2S OUTPUT port problem

Hello MaxDelius,

I have simulated your project with an exact setup here and I can successfully run it and get the outputs. I simulated it with two eval boards. The Rx project is the one that you have to test in your side. However, I will attach both working Tx and Rx projects here. Please run it in your hardware and get back to us, with that we will come to know whether there is a problem with the register settings or with the hardware. In my project I read and displayed the SPDIF lock register and the SPDIF does lock with the incoming signal. The SPDIF_Rx project is on ADAU1467; however, it will run on ADAU1466 without modification.

In the serial output port, you are running the port from CLKGEN3 that is the precision clock generator and you set the serial port rate as fs*2. Since you didn't attach your project, I don't know what the output of CLKGEN3 is. Is there any specific reason that you are using this?

You mentioned that the incoming BCLK to the serial input port is 6.03MHz, usually it will be 6.144MHz since 32*2*96000 = 6.144MHz. Are you using the on-board CODEC or an external one?

It seems like you are using our Eval board, so have you programmed the on-board SPI codec to run at 96Khz (since it defaults to 48Khz). I assume you had programmed it to work at 96KHz.

So, try this attached project and get back with your results. If you still have a problem, then please attach your project with your reply.

SPDIF_Rx_Tx at 96KHz.zip

Regards,

Harish

Hello Harish,

Thank you for your help and the files.

First, maybe I should describe my setup better.
I use an external AD converter from TI outputting a I2S signal with a sampling rate of 96kHz (BCLK 6.14 Mhz, LRCLK 96kHz, MCLK 24.576 Mhz). This is connected to my ADAU1466 evaluation board at Serial Input Port 3.
I also want to provide a SPDIF input which accepts sample rates up to 192 Khz and converts to the internal 96kHz using ASCR0.
On Serial Output Port 2 of the ADAU1466 Evaluation Board there is also an external DA converter and amplifier which expects a sampling rate of 96Khz (BCLK 6.144 Mhz, LRCLK 96khz, MCLK 24.576 Mhz). Everything including the ADAU DSP should be clocked by an external 24.576 Mhz master clock.
The internal signal processing in the ADAU1466 should also be done at 96Khz for now.

The 6.03 Mhz is of course not correct, I meant 6.14 Mhz for the BCLKs, sorry.

The use of CLKGEN3 has actually no specific reason. I just haven't achieved the desired output clock configurations with the other CLKGEN's when using an external master clock, unfortunately.
I tested your RX Configuration and indeed it works when I select as PLL Clk Source the PLL Clock.
How do I have to change my register configuration if I want to use an external MCLK with 24.576 Mhz ? Does this make sense at all or should I better use the PLL Clock ?

I get a pretty clean signal now after the Amp from the SPDIF Input now at 96khz. What registers do I have to modify to work with a 192khz SPDIF Input signal ?
Also since i got the digital input to work, the analog path is not as clean anymore as it was before, is there any compromise if i use both the analog and digital inputs ?

EDIT: It seems that the analog signal was much cleaner when using the external MCLK as PLL Clock source. 

The first picture shows the signal through : SPDIF IN -> ASCR0 -> DSP -> SerialOutput2 -> ext. DA Conv -> Amp -> DScope

The second picture shows the signal through : ext. AD-Conv -> SerialInput3 -> ASCR0 -> DSP -> SerialOutput2 -> ext. DA Conv -> Amp -> DScope

I also attached the project file.

Best regards,

Max

 SPDIF_rx_96KHz_1466_basic.dspproj.zip

Hello Max,

Thanks for the detailed information!

How do I have to change my register configuration if I want to use an external MCLK with 24.576 Mhz ? Does this make sense at all or should I better use the PLL Clock?

It's always recommended to use the PLL clock as a source to the core clock. I just wanted to make one thing clear here.

The register 0xF002 (PLL CLK SRC) is not actually named quite correctly. This register is not selecting the source to the PLL. It actually selects the source of the system clock. The max output of the PLL is 294.912Mhz. when you select 'PLL Clock' in the 0xF002 register then your system clock is 294.912MHz (if you set PLL CTRL1 as '4' (for 12.288MHz MCLK) or PLL CTRL1 as '8' (for 24.586MHz MCLK) and PLL CTRL0 as '96')

So, when you are bypassing the PLL (by selecting 'Direct from MCLK' in PLL CLK SRC) if your MCLK is 24.586MHz then that is your system clock. The DSP is running around 12 times lower than its nominal speed (294.912MHz). Then calculate the reduction in the MIPS for this system clock of 24.586MHz.

I get a pretty clean signal now after the Amp from the SPDIF Input now at 96khz. What registers do I have to modify to work with a 192khz SPDIF Input signal ?

Below is the place to change the register for SPDIF input at 192KHz. I will attach a project with all configs set for your application.

It has to be 'SYSCLK' as shown above.

Also since i got the digital input to work, the analog path is not as clean anymore as it was before, is there any compromise if i use both the analog and digital inputs?

I don't quite get this question; However, I don't think there has to be any compromise to get both of them to work fine. So, just verify the PLL clocking part that I mentioned above.

MaxDelius said:

SPDIF IN -> ASCR0 -> DSP -> SerialOutput2 -> ext. DA Conv -> Amp -> DScope

MaxDelius said:

ext. AD-Conv -> SerialInput3 -> ASCR0 -> DSP -> SerialOutput2 -> ext. DA Conv -> Amp -> DScope

But I can say, both of this above routing paths can be done and there shouldn't be any compromise to achieve this. Do you want anything other than this?

I have verified and exactly simulated both your routing paths, it all works well, and I have attached a project here. Please refer it.

ADAU1466_96khz_192khz spdif input.zip

Kindly do reply if want further questions.

Regards,

Harish

HI Harish,

Thanks again for your suggestions and answers, that was very helpful.
I now get a clean signal from the AD-Converter via Serial Input Port 3 by running it through ASRC1. If I don't use the ASRC there seems to be a problem with the timing and sampling. 
Unfortunately the 192kHz SPDIF Input doesn't work with both my own and your configuration in my setup, is there anything else I need to adjust ? The SDATA OUT seems corrupted on the scope although the clocks are correct.

Another question:
Is there anything against replacing the Toslink input with an XLR AES/EBU input by means of transformer coupling and level conversion/ Impedance matching?

Regards, 
Sebastian

Hello Sebatian,

Yes, using a transformer is a great solution. It is more costly so you do not see it often in production units. Have a look here:

Digital audio transformers • Lundahl Transformers

Can you put up your latest project? I would like to see how you are doing the clocking. Since one of your input signals is SPDIF, this means that it is not on the same master clock. So this usually means one of the two signals needs to use an ASRC or you need to switch the start pulse when you switch to the other signal. The start pulse is what synchronizes the program with the data coming into the DSP. It tells the DSP core when the frame is starting. I would also need to know what is clocking the ADC master clock input and where it is coming from? 

Dave T

Hi Dave, 

Yes you are right it is more expensive but since the development is aimed at the pro audio sector I definitely want to ensure operational reliability. The Lundal transformers are great, but quite pricey. I have also had quite good experiences with pulse electronic transformers for economical series production.

I have now managed, by setting the start pulse and adjusting the data rate on the serial audio output, to have the 192 kHz SPDIF signal through the ASCR0 on serial output 2 of the ADAU (and on the output of the amplifier).

I also run the signal from the AD-converter through ASRC1 and it works fine, without the ASRC its not working properly.

The AD Converter (and Amp, and DA Conv.) are all clocked by a dedicated 24.576 Mhz CMOS Clock. Could I use this clock also for the timing of the DSP ?

However, the looped signal from the SPDIF TX output is no longer registered as "locked" on the DScope at all sample rates, any ideas why ?

I have attached the current project file.

Concerning the AES XLR input and output, I would be interested in how this can best be solved circuit-wise. First of all, the DSP does not have a differential input for digital audio signals, so I thought about using a RS-485/422 differential bus transceiver after the transformer and level conversion to get a single-ended biphase signal at the RX Input.
The ADAU 1463/66 does not support the AES3 standards, so I wonder if I can simply loop the AES THRU signal through from the AES3 XLR input (and not through the DSP) to ensure signal encoding at the AES3 XLR THRU output when the signal comes from an AES3 source?
I would like to avoid to use a dedicated digital audio transceiver (like DIX9211 or similar) if possible.

Thank you,

S.

SPDIF_rx_96KHz_1466.dspproj.zip

Hello, 

Its been a while but now almost everything works as expected, except of the S/PDIF Through output signal at 192 kHz, i can't get it to lock on the DScope.
Processing a 192kHz signal from the S/PDIF and sending it to serial output port 2 (and to the dac, amp...) works fine, I can get a clean analog signal at the output of the amp. 

I want the S/PDIF output to be a simple copy from the input, but it only works up to 96 kHz. I also added an in- and output circuit to the evaluation board (see below) to alternatively use a transformer coupled RCA interface, but it works neither with the Toslink nor with the RCA interface at 192kHz.

Can someone maybe check if there is still a problem in the register map ? Maybe I am missing something obvious?
I attached my latest project file again.

Thanks and best regards,
Max

SC20X_SPDIF_and_Analog_Thru_1462.dspproj.zip