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Problem I2S bclk polarity with adau1466

Category: Hardware
Product Number: adau1466 eval board
Software Version: 4.6

first, sorry for this google traduction... I have a circuit which has this particularity: the i2s signal is generated by a type 45 logic CMOS circuit. When the spdif signal is 44.1khz no problem. When the spdif signal is 96khz the sound is degraded (significant noise). When I set the BCLK signal to "negative polarity" in serial_ports configuration it solves the problem. I don't understand, on the oscilloscope the signal seems correct in both cases, despite that I arrive at the limits of my oscilloscope which is 10 MHz, the spdif being 6.14 MHz.

The rising edges seem a little noisy because I use a breadboard, but this noise is identical in 44.1 and in 96khz. If anyone has a start I thank them in advance. Thank you !
  • I want to specify that I have to freeze the configuration,

    my project does not support the modification of the registers

  • Hello Paulo31,

    Are you receiving or transmitting the spdif signal?

    Can you please attach your project ?



  • Hello Paulo31,

    When using a breadboard it is very difficult to keep reflections and other signal integrity issues from becoming a problem. Then the data is not clocked in correctly due to noise and bad waveforms. Changing the BCLK polarity can fix this because it is reading in the data later in time but this is not the correct solution to the problem. 

    Since it works at 44.1kHz but not at 96kHz is the big piece of information that proves this. To be certain we should look at your sampling rate settings to provide your project so Harish or I can check it. 

    Also, I think you are using an SPDIF receiver IC that is sending the audio to the DSP as an I2S signal correct? Since you mentioned BCLK this means you are not using the SPDIF input of the DSP?

    Dave T