When I change the input divider to the PLL (CLK_CTRL2 bits 2:0) between the values of 0 and 1 it doesn't seem to change the clock rate?For verifying clock rates I am monitoring the MCLKO pin.
If I am running in integer mode on the PLL with a input divider of 1 and the integer divider of 2 I expect to have the same PLL output as having an input divider of 2 and an integer divider of 4. The issue is that these 2 examples seem to provide different outputs. The datasheet isn't super verbose about the values for the prescaler so could it be that a value of 1 is invalid and 2 is actually divide by 2? Sigmastudio doesn't appear to think this is true but maybe it is also following the bad assumption that I also made?