ADAU1463 TDM16 in slave mode

Question

Hello, 
 We use the ADAU1463 in a system with TDM16 signal 24/32 bits on 48kHz on Serial Port 0 from a FPGA but the dsp is not working correct as slave from this input 0. Every time the systems starts the timing is different. It seems that it is not using the LRCLK from Serial Port 0. I see data back from the DSP to the FPGA but after start up it is on a different place (not synchronized with the LRCLK) For the test I used a simple design with only 1 1kHz output on the first TDM slot, the position is different after each startup. (The codecs on the block schematics are not used for this test only the FPGA and DSP) The LRCLK to the Codec's is also not synchronized to the LRCLK from the FPGA

Are these settings correct or is TDM16 with the Slow Grade (150) version not possible with 24.576 MHz? 
 Regards, 
 Peter

Harishgowtham · Accepted Answer

Hi Peter, 
 Sorry for that, It's a silicon bug which was discovered and noted. It's only on the 150MHz core system clock variant like yours. The problem is the BCLK, if the BCLK frequency is over 12.288MHZ. 
 In your system , you are using TDM16 , so the BCLK = 32 * 16 * 48000 = 24.576MHZ. So it doesn't work as it's over 12.288MHZ. 
 If you use TDM8, 
 then the BCLK = 32 * 8 * 48000 = 12.288MHZ, So I hope it will work for you. 
 And the issue exists only when you use it as a slave. You can use that port as a master without an issue. In this, the clocks will be generated internally. These are the workarounds which we can suggest with this. 
 Regards, 
 Harish)

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ADAU1463 TDM16 in slave mode