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ADAU1463 TDM16 in slave mode

Category: Software
Product Number: ADAU1463 WBCPZ150
Software Version: Sigma Studio 4.6


We use the ADAU1463 in a system with TDM16 signal 24/32 bits on 48kHz on Serial Port 0 from a FPGA but the dsp is not working correct as slave from this input 0. Every time the systems starts the timing is different. It seems that it is not using the LRCLK from Serial Port 0. I see data back from the DSP to the FPGA but after start up it is on a different place (not synchronized with the LRCLK) For the test I used a simple design with only 1 1kHz output on the first TDM slot, the position is different after each startup. (The codecs on the block schematics are not used for this test only the FPGA and DSP) The LRCLK to the Codec's is also not synchronized to the LRCLK from the FPGA

Are these settings correct or is TDM16 with the Slow Grade (150) version not possible with 24.576 MHz?



  • Hi Peter,

    Sorry for that, It's a silicon bug which was discovered and noted. It's only on the 150MHz core system clock variant like yours. The problem is the BCLK, if the BCLK frequency is over 12.288MHZ.

    In your system , you are using TDM16 , so the BCLK = 32 * 16 * 48000 = 24.576MHZ. So it doesn't work as it's over 12.288MHZ.

    If you use TDM8,

    then the BCLK = 32 * 8 * 48000 = 12.288MHZ,  So I hope it will work for you.

    And the issue exists only when you use it as a slave. You can use that port as a master without an issue. In this, the clocks will be generated internally. These are the workarounds which we can suggest with this.



  • Hi Harish,

    In our system we need the TDM16 so I set the BCLK as master, and used a 12.288 MCLK as you can see in the blockdiagram below:

    The BCLK is disconnected from the FPGA and all Serial In/Outputs are set to master, only the 'LRCLK In 0' is set as slave-input to synchronize the DSP to the FPGA. Unfortunately this also does not work even if I set the TDM16 to TDM8. It is not possible in our system to lock the FPGA on the DSP.
    It seems that there is no way to use the LRCLK from the FPGA as startpuls for the DSP, or is there any setting that I missed? 

    Is the maximum frequency limitted to 12.288MHz which means that this device is not usable for our application with TDM16? (Startpulse is still set to 'Serial input 0 rate')

    In short: is there any way to work around the silicon bug in our system?

    (Original we used the ADAU1445 but because of availablity issues we made the switch to the ADAU1463- slow grade, also the normal grade has availability problems, so not a solution)