We use the ADAU1463 in a system with TDM16 signal 24/32 bits on 48kHz on Serial Port 0 from a FPGA but the dsp is not working correct as slave from this input 0. Every time the systems starts the timing is different. It seems that it is not using the LRCLK from Serial Port 0. I see data back from the DSP to the FPGA but after start up it is on a different place (not synchronized with the LRCLK) For the test I used a simple design with only 1 1kHz output on the first TDM slot, the position is different after each startup. (The codecs on the block schematics are not used for this test only the FPGA and DSP) The LRCLK to the Codec's is also not synchronized to the LRCLK from the FPGA
Are these settings correct or is TDM16 with the Slow Grade (150) version not possible with 24.576 MHz?