We have had multiple product failures from the field which are due to the ADAU1701 failing to start or maintain PLL lock.
This results in static noise being outputting on the DAC.
We have faced many issues with the PLL/Clock/Crystal design since conception:
1. Crystal Version
- Jan 2018 – PLL lock issues which were resolved by changing layout https://ez.analog.com/dsp/sigmadsp/f/q-a/64396/adau1701-1401-recommended-crystal-layout
However, 3 years later we again had product failures, - May 2021 – The crystal again failed to start-up which we reported but we received no conclusive response to forum post https://ez.analog.com/dsp/sigmadsp/f/q-a/544744/adau1701-dsp-crystal-stop-oscillating
We also experienced the PLL unlocked randomly after the PLL locked at startup.
To continue production we decided to change to an oscillator instead of a crystal which appeared to fix the issue.
- Jan 2018 – PLL lock issues which were resolved by changing layout https://ez.analog.com/dsp/sigmadsp/f/q-a/64396/adau1701-1401-recommended-crystal-layout
2. Oscillator Version ( Nov 2021). We have again have product failures but it is now losing lock intermittently e,g, 10minutes after power on, but we do NOT see startup issues like the crystal version.
Examining the fault, it looks highly likely that the ADAU1701’s PLL is going out of lock intermittently.
When measuring the PLL loop filter instead of seeing a constant DC voltage level we see it do periodic steps ~0.5V.
We can also see Pin19, Output BCLK, has large amounts of jitter corresponding to when Pin 46, DAC Out VOUT0 outputting static noise when the product faults.
The ADAU1701 has no way to read the PLL lock status to know for certain this is the fault. 
We have tried the following to try and determine what is causing the fault:
- Simplified the design to simple ADC0 -> DAC0 pass through in Sigma Studio
- Heating or cooling board has no effect on when the PLL loses lock
- Flexing PCB has no effect on when the PLL loses lock
- Changing PLL loop filter values (higher and lower) has no effect on correcting PLL loss of lock
- Check power supplies for noise and tried powering directly from lab supply
Can you please advise what we can do to debug the PLL.
Below is a schematic capture of the current design and PCB layout.
Also included is a capture of the oscillator output at R195.
