eval-adau1467Z rev. B documentation

Hello Frank,

The ADAU1467 Rev B evaluation board fixes only minor issues with the Rev A board, and almost everything in the existing user guide will apply to Rev B. Some reference designators for resistors, caps, etc. may be off, but everything else applies.

There were some changes to the schematics from Rev A to Rev B; I will attach the Rev B schematic to this post. I'm also attaching a SigmaStudio project with all the analog I/O preconfigured for the ADAU1467 eval board.

If you have any trouble with this board, please let us know.

Best regards,

Joshua

PDF7737.Example IO Project - EVAL-ADAU1467Z.zip

Hello Joshua,

Thank you for your reply and the updated schematic.

I do have the board fully working at 192kHz and with four additional stereo DACs. It was while adding these I noticed a few differences compared to UG-1134 such as the omission of S5, S6 & S8 and the move of power from J8 and CLKOUT from J9 to a new header J4, hence my question as to whether an update was available. The new schematic seems to tally with the board now

Best regards,

Frank

Hello Joshua,

Thank you for your reply and the updated schematic.

I do have the board fully working at 192kHz and with four additional stereo DACs. It was while adding these I noticed a few differences compared to UG-1134 such as the omission of S5, S6 & S8 and the move of power from J8 and CLKOUT from J9 to a new header J4, hence my question as to whether an update was available. The new schematic seems to tally with the board now

Best regards,

Frank

Hello Joshua,

I thought I was getting along fine with the board but I'm going to have to give in and ask for help with the ADC in the AD1937. I'm trying to run at 192KHz sample rate and the DACs are ok, as are some external DACs I've added on. The first ADC pair seem to work ok, sine wave = sign wave out. However, the second ADC pair does not work correctly, I get this:

Signals at the + and - inputs to the ADC are fine.

I've searched this Zone to check for information and settings but am having difficulty in making sense of the terse datasheet Clock Signals section description and the register settings. I used one of the AD engineers examples "SigmaDSP Programming CODEC via I2C to 192 kHz" for setting the AD1937 registers, etc. but to no avail. One thing odd in the example, but perhaps not relevent as it is a DAC setting, is DAC Control 2 = 0x40, meaning that bit 6 is set. According to the datasheet bits 7:6 are reserved and should be 00.

I'm really puzzled how the first ADC pair work fine but not the second as I do not see any settings to affect individual ADCs other than mute.

Although I have tried many settings, these are my current ones, grabbed by probing the I2C lines directly to make sure of what is being sent:

Have include my test project file, any help will be greatly appreciated.

Best regards,

Frank

PS: I should add that the ADCs work fine at 48kHz

SigmaDSP Programming CODEC via I2C to 192 kHz.dspproj

Hello Frank,

Thanks for posting a screenshot of the wave form. This is the case where the sign bit is getting lost in transmission. I would normally say it can also be a difference in the settings between the sending device and the receiving device but since you said the first SDATA out works fine but the second does not, and then added that it all works fine at 48kHz pretty much tells me that it is a transmission/signal integrity issue. 

At 192kHz it can be difficult to transmit for any distance especially from one board to another. In the lab we always have difficulty at this high rate when connecting between boards or to the Audio Precision test equipment. 

What is happening is that the sign bit is not being picked up, the MSB before the sign bit is being picked up at the sign bit. I will use bit 23 as the sign and bit 22 as the MSB. This would be so if you start counting the bits from bit zero. So now it is all fine as long as the level is not close to the max level. If you look at the 2's compliment number, when the level is low and it is a positive number the upper unused bits are all zeros. 

When the level is low and it is a negative number all the upper unused bits are ones. So if bit 23 is missed and bit 22 is used as the sign bit you cannot notice the issue. 

When the signal level gets high enough in a positive direction to set bit 22 to a one, Well, the receiving device suddenly sees a negative number so the last part of the positive peak of the sine wave starts going negative. 

Then on the negative side the opposite happens. Bit 22 is a one until the negative level gets high enough to set bit 22 to a zero so all of a sudden the sine wave is a positive number so the rest of the peak is a positive going waveform. 

Fixing this might be difficult. The SDATA and BCLK are the two lines that are important to run short and it is usually a good idea to use a ribbon cable with ground running along with it between each signal or just a two conductor ribbon with ground and the clock/data.  You might have to increase the drive strength of the pins that are driving the LRCLK, BCLK and SDATA. You might also need to put in a series resistor to damp down any reflections especially if you increase the drive strength. Increasing the drive strength will decrease the rise and fall times giving more timing margin to not miss that very important first bit. If the SigmaDSP is the master for the clocks then there are registers to adjusting the drive strength. For the AD1937 there is no adjustment, it is an older part and we had not started adding that feature. 

So this should give you a start on figuring this out. 

Dave T

Hello Dave,

Thank you for your detailed reply. Just one problem though re lead lengths, resistors, etc. - this is on the EVAL-ADAU1467Z Rev. B board, not my own design.

I have since had it working fine at 96kHz as well as 48kHz.

Are you able to test this on the Rev. B evaluation board?

KInd regards,

Frank

Hello Dave,

I took some more measurements and although it may be a sign problem I don’t think it is how you described because if it were to be then wouldn’t a small amplitude input look ok?

 For reference, here is the first SDATA with a ramp at 50Hz. (I used a low frequency as at higher frequencies propagation delay confuses things.)

There is quite some non-linearity showing but I found this to be a low frequency response issue in the input circuit on the EVAL board as it appears at ADC[L|R][1|2]][P|N] input pins.

Same signal on second SDATA:

Now with the input signal reduce to 10%:

I have found a way to get both SDATA inputs working at 192kHz which is to change the Serial Input Port BCLK signal from default of negative edge to positive edge.

Looking at the BCLK, LRCLK and both SDATA lines, I was surprised to see both SDATA lines transmitting in the same phase of the 192kHz LRCLK, is this to be expected?

The second SDATA is the red trace. Changing the BCLK phase does shift the data slightly later relative to LRCLK, perhaps confirming your theory of the negative sign getting missed.

Kind regards,

Frank

Hi Dave,

Sorry for the bombardment of messages, but I think I’m getting somewhere now. It would seem that in order for the DSP to look at both SDATA inputs from the ADC the Serial Input Port 2 needs to be set at 4 channels, 32 bit/channel, which is what I have been doing so far. But this causes the BCLK rate to double which in the case of 192 kHz sample rate becomes 24.576 MHz so it is no wonder the sign bit was going missing – in fact I’m surprised it worked at all!

By setting Serial Byte 1 to Fs/2 the BCLK frequency drops to 12.288MHz which for 32 bit stereo data would be correct (64 bits x 192 kHz).

This does beg the question as to what is going on versus what is supposed to happen? My understanding of using two SDATA lines is to save having to increase the bit clock frequency by a factor of two. But if my findings above are correct, then half the available data bandwidth is not being used.

What seems to be missing in SigmaStudio is an ability to set two I2S stereo channels because setting TDM4 mode is the only way to see data from the second SDATA line.

EDIT: Just realised that LRCLK also halved, so the above is not a correct working solution. Hence the current question must be: What settings are required to get 192kHz sampling rate with 12.288 MHz BCLK? This is what I would expect to be able to achieve if using SDATAIO pin to supplement the SDATA pin, otherwise what is the benefit over using SDATA only in TDM4 mode?

As a workaround, I have used SDATA_IN1 for the second AD1937 output. This was easily achieved on the EVAL board by taking a short wire from MIC CANVAS pin 8 to the SDATA_IO4 test point.

In the process, I've noticed an error in the circuit diagram in the UG-1134 document and also the updated circuit Joshua added to this thread above. Both circuits have SDATA_IN1 and LRCLK_IN1 (after the resistor) transposed where they go into the DSP. Fortunately the PCB layout is correct!

Kind regards,

Frank

Hello Frank,

You have run across a bug in the silicon that has a work around. Here is more info:

(9) ADAU1467 SDATA IO not working - Q&A - SigmaDSP Processors and SigmaStudio Development Tool - EngineerZone (analog.com)

There are other posts that has links in this post but I think Ken and Josh's answers should be able to help you. 

Dave T

Hi Dave,

Thank you for your reply and link, I did not come across that in my search before posting.

If I understand the proposed workaround correctly, it is suggested to supply either BCLK ot LRCLK from a different port with BCLK at half or LRCLK doubled. As this would need a hack to the EVAL PCB to cut a trace between the DPS and CODEC and also uses another port, I think I'll stick to my easier solution of hardware fix by just taking the second SDATA from the CODEC into SDATA_IN2 and running both input ports in 2 channel mode.

Frank