LRCLK in TDM8

Hi,

I have a device connected to an ADAU1466 that transmits audio with a kind of TDM8 where the period of the LRCLK signal has a duration of 2 channels instead of 8.
In practice it is an I2S where in the first frame there are channels 1 and 2, in the second 3 and 4, in the third 5 and 6, in the fourth 7 and 8, and then it is repeated.
The question is whether there is a way to configure the port of the DSP, or whether it is possible to separate the channel samples within the DSP.

Thanks and best regards,

Alessandro.

  • 0
    •  Analog Employees 
    on Oct 11, 2021 9:06 PM

    Hello,

    If I'm understanding correctly, your ADAU1466 is acting as a clock slave and the format looks like this drawing:

    This is really a strange format, and to me it seems flawed. Let me explain why. It has to do with the clocking mechanisms of I2S/TDM.

    Normally LRCLK determines which channel of a TDM8 stream is "Channel 0". By searching for the LRCLK edge and then counting how many BCLK cycles have taken place, the I2S/TDM receiver can determine where it is in the frame and assemble the channels in the right order.

    On the ADAU1466, If LRCLK is set to negative polarity, the DSP waits for a falling edge and, whenever it appears, transfers the current frame of audio to the next buffer and clears the serial input port shift register. This will become important if you can work around what I am about to describe. If LRCLK is set to positive polarity, this happens on the rising edge. Either way, one period of LRCLK corresponds to one frame of audio

    If LRCLK has multiple cycles in one frame, the DSP has no reference to differentiate between channels 0, 2, 4, and 6.

    Each time the DSP starts up, it will have a 25% chance of the correct stream appearing as Channel 0. In the other 75% of cases, it will appear as Channel 2, Channel 4, or Channel 6.

    If you can think your way around this issue, we can move on to dealing with the rest of the configuration, which will involve:

    • Sampling the serial ports at quad speed
    • Locking Start Pulse of the DSP core to this TDM8 input
    • Running the DSP core at quad speed (in order to keep up with the LRCLK transitions)
    • Untangling each channel's data in the DSP by using counters, multiplexers, and sample-and-hold blocks
    • Downsampling each channel in the core for processing at standard audio rates

    Good luck!

    Joshua

  • Thanks for the reply.
    I think the LRCLK problem can be solved somehow. Audio signals are generated by software, and this software may generate an LRCLK enable signal the first time channel 0 is exited.
    Rather, I understand that the solution inside the ADAU is not easy and that there is a risk that I will not have enough resources left for the rest of the audio processing.

    I have to understand if there can be another solution, for example to insert an fpga that converts the audio signals to a standard TDM8.

    Thanks again,

    Alessandro.

  • 0
    •  Analog Employees 
    on Oct 27, 2021 11:57 AM in reply to alrouge

    Hi Alessandro,

    My apologies for the delay. Your suggestion of generating an LRCLK enable signal will probably work.

    Although if you have control over the software generating the audio signals, I would think the TDM source could generate the proper LRCLK frequency from the beginning. What is the TDM source you are using? Are you sure there is no way to adjust the LRCLK generator?

    Even if you have no control over the LRCLK source frequency, I think FPGA glue logic is overkill for this application. It is well within the DSP's capability to sort through the channels in the core, and my educated guess is that this would use less than 5% of the available cycles.

    Best regards,

    Joshua