ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work

Hi,

i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0.

SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK domain 0. In this configuration i never get a signal out of SDATA_OUT3.

As i understand the datasheet every output port can be referenced to any clockdomain as slave. This seems to be a very basic task but i don't get it working.

The same behaviour with ADAU1467.

Any idea what i am doing wrong or what i am misunderstanding?

  • +1
    •  Analog Employees 
    on Aug 9, 2021 2:51 PM in reply to Beni

    Hello Bernd,

    If you have clocks supplied to the LRCLK_OUT_3 and BCLK_OUT_3 pins then you have set serial output port 3 to be a slave from clock domain 3, then you will get output on SDATA_OUT_3 provided you are sending data to that port. There is no hardware issue with the part. There is no design flaw. What I discussed in my earlier post is also not a design flaw. 

    If you have valid clocks on those pins and have it set to slave from domain 3 then there is an issue with how you are routing data to that serial port. In addition I need to say that you will HAVE to go through a sample rate converter with this configuration. The audio will not be correct if the core is running on an internal clock that is running off of a different master clock. 

    Now, am I missing something here? You have clocks coming into the output port 3 clocks that are asynchronous and you do not want to use these clocks. You want SDATA3 to use the internal clocks but if you do there will be a clash of clocks on the pins when you set it to master. Is that your problem? 

    As a temporary solution you could externally jumper the LRCLK_0 and BCLK_0 pins over to either serial output port 1 or 2 and then set serial port 3 to be a slave off of one of those clock domains. That would work. 

    Why don't you zip up your project and post it. It will save a lot of time since I can check many things in the same time it took me to write this post. 

    Dave T

  • Hello Dave,

    Now, am I missing something here? You have clocks coming into the output port 3 clocks that are asynchronous and you do not want to use these clocks. You want SDATA3 to use the internal clocks but if you do there will be a clash of clocks on the pins when you set it to master. Is that your problem?

    Yes exactly that is my situation. And yes i can jumper the clocks or change the port. I allready changed the hardware and moved the clock to an other port.

    As a résumé i have to connect my clocks more carefully because the clock and data pins are not completely independent.

    Thanks for helping

    Bernd