ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work

Hi,

i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0.

SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK domain 0. In this configuration i never get a signal out of SDATA_OUT3.

As i understand the datasheet every output port can be referenced to any clockdomain as slave. This seems to be a very basic task but i don't get it working.

The same behaviour with ADAU1467.

Any idea what i am doing wrong or what i am misunderstanding?

Parents
  • +1
    •  Analog Employees 
    on Jul 30, 2021 4:00 PM

    Hello all,

    The answer is very simple. The pin pads internally have clock inputs from the internal clocks. Then there are four buss to go between the four serial output ports ( and the same thing for the four serial input ports but they are not connected) So the pads can output a clock out onto one of these buss or take the signal from one of the buss as an input. 

    When a pin is set to be a slave, it will take the external clock coming in and send it out on the buss so the other clock pins can pick it up. 

    Well, the designers designed the pin pad such that when it is set to be a master, it takes the internal clock and sends it out of the pin but NOT out onto the buss for other pins to pick up. The reason for this is that if you want the other pins to be running off of the same clock then just set those pins to be a master. There is no reason to take the clock from the buss when it will be subject to a little delay through the extra circuits that drive the buss. The other pins have direct access to the same internal clock. 

    So in this example, you must set the serial ports 1-3 as masters. You still can use the LRCLK pins for ports 1-3 as MP pins and the serial ports will still work. 

    Brett, you are correct in that if you slave off of an external clock you can set the DSP start pulse to be one of the serial input ports or one of the serial output ports. Then if you have the serial input and output ports slave to this external clock, then you do not have to use the ASRC and they also do not even have to be on the same master clock. Just make sure the clocks never go away because if you do the DSP program stops in its tracks until it sees another start pulse.

    If they are on the same master clock then you could have the start pulse running on an internal clock and the clock jitter circuits will align up and clock edge differences and it will run fine. Because they are all on the same master clock. 

    I hope this helps.

    Dave T

  • Hi Dave,

    Yes it seems to be as you explained. But when you set an output pin as master the corresponding LRCLK and BCLK are also set as master.

    In my case i want to output signal on SDATA_OUT3 with the internal dsp clock but unfortunatly i have connected an asynchronous clock to the LRCLK3 and BCLK3. So SDATA_OUT3 as master does not work and SDATA_OUT3 set as slave does not work either. Ok i can fix this in hardware for the next version but i expected that it could be solved in software.

    I would welcome any ideas to solve this problem.

    Thank you for taking the time to look into this problem Dave.

    Bernd

  • +1
    •  Analog Employees 
    on Aug 9, 2021 2:51 PM in reply to Beni

    Hello Bernd,

    If you have clocks supplied to the LRCLK_OUT_3 and BCLK_OUT_3 pins then you have set serial output port 3 to be a slave from clock domain 3, then you will get output on SDATA_OUT_3 provided you are sending data to that port. There is no hardware issue with the part. There is no design flaw. What I discussed in my earlier post is also not a design flaw. 

    If you have valid clocks on those pins and have it set to slave from domain 3 then there is an issue with how you are routing data to that serial port. In addition I need to say that you will HAVE to go through a sample rate converter with this configuration. The audio will not be correct if the core is running on an internal clock that is running off of a different master clock. 

    Now, am I missing something here? You have clocks coming into the output port 3 clocks that are asynchronous and you do not want to use these clocks. You want SDATA3 to use the internal clocks but if you do there will be a clash of clocks on the pins when you set it to master. Is that your problem? 

    As a temporary solution you could externally jumper the LRCLK_0 and BCLK_0 pins over to either serial output port 1 or 2 and then set serial port 3 to be a slave off of one of those clock domains. That would work. 

    Why don't you zip up your project and post it. It will save a lot of time since I can check many things in the same time it took me to write this post. 

    Dave T

Reply
  • +1
    •  Analog Employees 
    on Aug 9, 2021 2:51 PM in reply to Beni

    Hello Bernd,

    If you have clocks supplied to the LRCLK_OUT_3 and BCLK_OUT_3 pins then you have set serial output port 3 to be a slave from clock domain 3, then you will get output on SDATA_OUT_3 provided you are sending data to that port. There is no hardware issue with the part. There is no design flaw. What I discussed in my earlier post is also not a design flaw. 

    If you have valid clocks on those pins and have it set to slave from domain 3 then there is an issue with how you are routing data to that serial port. In addition I need to say that you will HAVE to go through a sample rate converter with this configuration. The audio will not be correct if the core is running on an internal clock that is running off of a different master clock. 

    Now, am I missing something here? You have clocks coming into the output port 3 clocks that are asynchronous and you do not want to use these clocks. You want SDATA3 to use the internal clocks but if you do there will be a clash of clocks on the pins when you set it to master. Is that your problem? 

    As a temporary solution you could externally jumper the LRCLK_0 and BCLK_0 pins over to either serial output port 1 or 2 and then set serial port 3 to be a slave off of one of those clock domains. That would work. 

    Why don't you zip up your project and post it. It will save a lot of time since I can check many things in the same time it took me to write this post. 

    Dave T

Children
  • Hello Dave,

    Now, am I missing something here? You have clocks coming into the output port 3 clocks that are asynchronous and you do not want to use these clocks. You want SDATA3 to use the internal clocks but if you do there will be a clash of clocks on the pins when you set it to master. Is that your problem?

    Yes exactly that is my situation. And yes i can jumper the clocks or change the port. I allready changed the hardware and moved the clock to an other port.

    As a résumé i have to connect my clocks more carefully because the clock and data pins are not completely independent.

    Thanks for helping

    Bernd