ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work


i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0.

SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK domain 0. In this configuration i never get a signal out of SDATA_OUT3.

As i understand the datasheet every output port can be referenced to any clockdomain as slave. This seems to be a very basic task but i don't get it working.

The same behaviour with ADAU1467.

Any idea what i am doing wrong or what i am misunderstanding?

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  • Sorry My reply was for Beni

    Brewster, your question is really determined to how you have wired all the slaves

    I assume all 4 ports are slaves?. if all 4 Master devices are again Clocked from the SAME MCLK then you can choose any of the 4 clock domains (provided all 4 masters  LRCLK /  BCLK are in sync)

    If you set the StartPulse to the "Serial out rate 0" then the DSP is clock at the same rate and you wont need SRC