ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work

Hi,

i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0.

SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK domain 0. In this configuration i never get a signal out of SDATA_OUT3.

As i understand the datasheet every output port can be referenced to any clockdomain as slave. This seems to be a very basic task but i don't get it working.

The same behaviour with ADAU1467.

Any idea what i am doing wrong or what i am misunderstanding?

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  • I don't have an answer but interested in what the official answer is as I seem to have the opposite situation. I'm using all 4 SD outs in the same clock domain (OUT0) but I never changed the SERIAL_PORT settings to make domains 1-3 slaves of 0, and yet it works where the data is matched to LRCLK0, etc.

    To me what you did sounds like what I should have done.

Reply
  • I don't have an answer but interested in what the official answer is as I seem to have the opposite situation. I'm using all 4 SD outs in the same clock domain (OUT0) but I never changed the SERIAL_PORT settings to make domains 1-3 slaves of 0, and yet it works where the data is matched to LRCLK0, etc.

    To me what you did sounds like what I should have done.

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