i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0.
SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK domain 0. In this configuration i never get a signal out of SDATA_OUT3.
As i understand the datasheet every output port can be referenced to any clockdomain as slave. This seems to be a very basic task but i don't get it working.
The same behaviour with ADAU1467.
Any idea what i am doing wrong or what i am misunderstanding?