EVAL-ADAU1452 - distortion on i2s inputs

Hi there,

I have an external i2s source which I connected to my logic analyser to confirm a solid digital signal:

It shows a 3MHz SCLK, 48kHz LRCLK and the i2s analyser gets good 24-bit data values.

I then move the 4 cables from my logic analyser to the IN2 header pins on the EVAL-1452 board, but when I listen to the audio output it is distorted and sounds almost like it is pulsing noise at 3-4 Hz.  You can sort of hear some of the content from time to time. 

Test file

Obviously there is something wrong in my setup.  I tried to also route serial input 2 to ASRC0, the output of which sounds the same as just grabbing the serial 2 input.  The gain sliders have no effect over the output volume.  One channel is noticeably louder than the other.

I have attached my SigmaStudio test file also.

I hope you can help!  Many thanks!  Slight smile

i2s test project - Sigma Studio Project.zip

Parents
  • 0
    •  Analog Employees 
    on Jul 22, 2021 7:32 PM

    Hello MDThommo81,

    This is a clocking issue. Usually a Dante source is a clock master is my understanding. It does not have the ability to buffer the audio and if the sampling rates were really different it would either run out of data or the buffer would overflow. I am guessing that when you connected the Dante output to your logic analyzer you were sending clocks from the Dante to the analyzer. 

    So you need to setup the DSP in a similar way. So it will slave to the incoming Dante clocks. If this is going to be your entire system then it is simple. If you will have other sources of audio from other clock domains then you will have to stand back and look at all your clocking to design a system that works. This is a bigger discussion so I will focus on the simple task at hand. 

    First, you have the serial input port 2 set to be a master. So you have clocks fighting clocks and that is never a good thing. It gets a little bloody. :)

    So set the serial port to slave to serial port 2 clock domain. 

    Do the same for the BCLK right below it. 

    So that will get the data to clock into the shift register correctly. 

    Now, lets work on getting the DSP core and the Serial Output to work. 

    This brings up another question that you did not address. Where is the output going to? How is it clocked? I see that you have an AD1938 in your config so I assume that is what you are using for DACs. They are connected to serial ports 0,2 & 3 according to your schematic output assignments and on the serial port configuration page I see those are set to be a master. I assume the DSP and the Codec are on the same master clock domain.

    So this means that the DSP and the DAC are on its own domain and will not be running at the Dante domain clocks. So this means you must use an ASRC to adapt the Dante rate to the DSP and Codec rate. 

    You have the ASRC setup to use the internal fs domain.

    This will work fine. 

    So in your schematic you will need to use the ASRC input into the core and not the serial port directly. You will notice that there will be a difference once you have the clocks setup. 

    So I think your issue was the serial input port 2 not set to be a slave. 

    Dave T

  • Thanks, Dave,

    Almost there I think...  Your assumptions are correct.  Since I'm testing this on my EVAL-ADAU1452REVBZ board I'm using the onboard codec as my outputs.

    Setting serial input 2 as slave and using ASRC0 at the input has resulted in more "audio-like" sound but now it sounds very loud and distorted...  

    Still can't put my finger on what is causing this. Could it be in the control of the Codec? I tried settings of the SDATA_OUT2 serial output ports but nothing...  It all goes silent when I attempt to set BCLK Source and LRCLK Source to clock domain 2, is that a clue?

    I'm listening to the output on the Eval board using headphones connected to "OUT3".

    I've simplified my test project file and attached here.  Is there anything you notice?Test 2CH Dante I2S inputs_v2.zip

  • 0
    •  Analog Employees 
    on Jul 27, 2021 6:48 PM in reply to MDThommo81

    Hello MDThommo81,

    Your project was helpful. When you switched to the internal noise source it also had the same issue with it being really loud and mostly in one channel. I found that the serial output port 0 was set to fs/4. This drives the codec DACs so it was getting the wrong rate. I switched it to fs and the noise source now sounds great. 

    I did not try it with an external I2S source but I am confident it will work now. 

    I did notice that you had the codec setup in the hardware config. The codec on this eval board is running in standalone mode so you cannot control the codec. I did document in the user guide how you can modify the board to have control of the codec. Did you perform that mod?

    Dave T

  • Hi Dave,

    Yes, I modified the board as per your instructions in the user manual so I can have control over the codec on the evaluation board.

    That Serial Port you have highlighted is SDATA_OUT0, my headphones are connected to outputs 32,33 on SDATA_OUT2 which had a sampling rate already set to Fs.

    Also, when I run the Noise source, it meters at -5dBFS.  Still sounds terrible on the headphones.  I note that there is no impact of the volume controller between 0 dBFs and -44 dBFS.  In that range there is no increase in audible level, and the output meters -49 dBFS.  As I increase the fader from -44 to 0dBFs the output meters show the signal level increasing, but as I mentioned, the audible level doesn't change. 

    Output 33 has a very low audible level.  Using my codec controls, muting Channel 3L and then Channel 3R indicates that the low level noise is on both outputs as I can hear them mute on my headphones.  

    Output 32 has the high level audible output.  And again using the codec controls I can hear the noise on both output channels too...  So that seems a tad strange....

  • +1
    •  Analog Employees 
    on Jul 28, 2021 3:14 PM in reply to MDThommo81

    Hello MDThommo81,

    Glad you did the mod! I went through a lot of effort to get that in the user guide. I just looked for my board and it is back in my home office and we are now back to working in the office. I still have some things home so I cannot test it here at the moment with your exact setup. 

    But, let me show you why I made the comments I made and I did experience the same issues you did. 

    Here is a screenshot of your project unchanged:

    Note that serial output port 0 is set to fs/4

    When I change it to fs it works great. 

    This is why. Here is a screenshot of the codec page of the eval board schematic 

    Note that the DAC section of the codec is clocked by the serial output port 0

    The other three serial output port clocks are not being used for clocking. The LRCLK pins are brought out to be used as MP pins and the bit clock pins just go to test points and nowhere else.

    That is seen here:

    So serial port 0 clock rate is what matters for driving the codec. The other three settings matter for clocking out the bits but not for actually driving the codec. So the settings will still matter and they do need to be set to be a master but this is only so that there will be data on SDATA_OUT1,2 & 3

     Dave T

Reply
  • +1
    •  Analog Employees 
    on Jul 28, 2021 3:14 PM in reply to MDThommo81

    Hello MDThommo81,

    Glad you did the mod! I went through a lot of effort to get that in the user guide. I just looked for my board and it is back in my home office and we are now back to working in the office. I still have some things home so I cannot test it here at the moment with your exact setup. 

    But, let me show you why I made the comments I made and I did experience the same issues you did. 

    Here is a screenshot of your project unchanged:

    Note that serial output port 0 is set to fs/4

    When I change it to fs it works great. 

    This is why. Here is a screenshot of the codec page of the eval board schematic 

    Note that the DAC section of the codec is clocked by the serial output port 0

    The other three serial output port clocks are not being used for clocking. The LRCLK pins are brought out to be used as MP pins and the bit clock pins just go to test points and nowhere else.

    That is seen here:

    So serial port 0 clock rate is what matters for driving the codec. The other three settings matter for clocking out the bits but not for actually driving the codec. So the settings will still matter and they do need to be set to be a master but this is only so that there will be data on SDATA_OUT1,2 & 3

     Dave T

Children