EVAL-ADAU1452 - distortion on i2s inputs

Hi there,

I have an external i2s source which I connected to my logic analyser to confirm a solid digital signal:

It shows a 3MHz SCLK, 48kHz LRCLK and the i2s analyser gets good 24-bit data values.

I then move the 4 cables from my logic analyser to the IN2 header pins on the EVAL-1452 board, but when I listen to the audio output it is distorted and sounds almost like it is pulsing noise at 3-4 Hz.  You can sort of hear some of the content from time to time. 

Test file

Obviously there is something wrong in my setup.  I tried to also route serial input 2 to ASRC0, the output of which sounds the same as just grabbing the serial 2 input.  The gain sliders have no effect over the output volume.  One channel is noticeably louder than the other.

I have attached my SigmaStudio test file also.

I hope you can help!  Many thanks!  Slight smile

i2s test project - Sigma Studio Project.zip

  • Just had a quick comparison with mine, and noticed you have serial input 2 set to 32 bit word length?

  • Yeah, that's probably where I left it.  I was changing the word length when trying to get it to work...  24-bit didn't work either...  Disappointed

  • Ok, start from scratch.

    Do you get a clean output if you have an oscillator instead of an input?

    Have you checked that the act of connecting to the board isn't messing up your signal? (e.g. rogue pull up/down)

    I'm pretty sure the attached worked when I was initially testing, if you want to try it.

    ADAU1452_Multi-Input XO v1.zip

  • Looking at mine, I think you might want to try disabling all the pull-downs on the PIN_DRIVE tab

  • 0
    •  Analog Employees 
    on Jul 22, 2021 7:32 PM

    Hello MDThommo81,

    This is a clocking issue. Usually a Dante source is a clock master is my understanding. It does not have the ability to buffer the audio and if the sampling rates were really different it would either run out of data or the buffer would overflow. I am guessing that when you connected the Dante output to your logic analyzer you were sending clocks from the Dante to the analyzer. 

    So you need to setup the DSP in a similar way. So it will slave to the incoming Dante clocks. If this is going to be your entire system then it is simple. If you will have other sources of audio from other clock domains then you will have to stand back and look at all your clocking to design a system that works. This is a bigger discussion so I will focus on the simple task at hand. 

    First, you have the serial input port 2 set to be a master. So you have clocks fighting clocks and that is never a good thing. It gets a little bloody. :)

    So set the serial port to slave to serial port 2 clock domain. 

    Do the same for the BCLK right below it. 

    So that will get the data to clock into the shift register correctly. 

    Now, lets work on getting the DSP core and the Serial Output to work. 

    This brings up another question that you did not address. Where is the output going to? How is it clocked? I see that you have an AD1938 in your config so I assume that is what you are using for DACs. They are connected to serial ports 0,2 & 3 according to your schematic output assignments and on the serial port configuration page I see those are set to be a master. I assume the DSP and the Codec are on the same master clock domain.

    So this means that the DSP and the DAC are on its own domain and will not be running at the Dante domain clocks. So this means you must use an ASRC to adapt the Dante rate to the DSP and Codec rate. 

    You have the ASRC setup to use the internal fs domain.

    This will work fine. 

    So in your schematic you will need to use the ASRC input into the core and not the serial port directly. You will notice that there will be a difference once you have the clocks setup. 

    So I think your issue was the serial input port 2 not set to be a slave. 

    Dave T