ADAU1467 SDATAIOx problem

Hi,

I have a project that needs to use SDATAIOx of ADAU1467 to expand four I2S inputs. I can't use SDATA_IN0/1/2/3. Because my project has decode board (4 I2S inputs), Bluetooth (1 I2S input), ADC (2 I2S inputs).

According to the datasheet of ADAU1467, SDATA_IN0 (Serial Input Port0) needs to be configured as 4 channels. But the clock combination of SDATA_IN0 is LRCK=48K and BCLK=6.144M, which is not the standard I2S format(LRCK = 48K, BCLK = 3.072M).

 

So, is there any other way to solve my needs? Thanks!

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  • 0
    •  Analog Employees 
    on Jul 8, 2021 7:27 PM

    Hello,

    This is a bug in the firmware of the part. You have to set it for 4 channels on the serial input port. Note, this is not an issue with the serial output port. Since it is s slave it will take the slower bitclock from the I2S just fine and the data will appear in the correct place. 

    You have four I2S inputs which is 8 channels of audio. The serial port will be configured to take in 4 channels on each pin which is 16 channels and it will be a clock slave. With the bitclock being half the speed you will only clock in two channels on each pin then the frame will end and all is reset to start over. Since all you need to clock in is two channels per pin it all works fine. 

    Dave T

  • Hi Dave,

    Sorry, I don't quite understand what you said.

    In my project, the decoder board is the master, and outputs four I2S (48K, 3.072M) signals. ADAU1467 is the slave. I have tested many times, no matter how I configure Serial Input Port0, SDATAIO0/1/2 will not work correctly. Only SDATA_IN0 works properly. On SDATAIOx, there is only left channel input and no right channel input.

    Thanks!

  • +1
    •  Analog Employees 
    on Jul 15, 2021 3:11 PM in reply to fjlasjdfkj322038402

    As Dave said, this is a bug and can be a little confusing. The need to set the serial port as TDM4 only applies when the DSP is a clock slave. As you correctly note, if you use that setting when the DSP is a clock master, it will output a BCLK at twice the desired rate. In short, when the DSP is sourcing BCLK, use the settings that you would expect, two channels, for I2S.

    When the DSP is a clock slave, as in your case, the DSP is being told to expect four channels per frame (i.e. 128 BCLKs), but it will only receive the two channels (64 BCLKs) of data as used in standard I2S. Internally, the SPORT input is just a shift register latched by the incoming BCLK. The result is that the transmitted two channels are latched into the first 64 bits, then the transfer is interrupted by the next LRCLK transition. At this transition, the contents of the shift register are latched into the core, the register is cleared, and the next frame begins. Since you only require the first two channels, the "missing" data for the second half of the four channel frame is unused and ignored. 

    The settings above should work. The problem may be elsewhere in your project. PULSE_START is an obvious candidate. If you can, please post your full project, and we'll take a look. If you would prefer not to, DM me and I'll look at it offline.

    Ken

  • Hi Ken,

    Thank you very much! Your reply is very helpful to me. I seem to fully understand how it works. And my problems have been fixed. In this TDM4 configuration, channels 2 and 4 are missed.

    Thank you and Dave.

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