I have a setup with a ADAU1467 DSP feeding into 5 D/A converters with 4 channel each. The D/A converters expect TDM128 with bclk 512fs and negative bclk polarity (falling edge on falling edge) 32bit/channel and 32bits with i2s compatible output.
The ADAU1467 is driven by external MCLK with 44.576 MHz.
I experience 3 problems (maybe related to each other?):
- no matter what I select for serial output blck polarity it does not alter the signal. Falling edge of data is always on rising edge of blck
- I must set the clock gen1 to 6/7 for n and m; otherwise blck is too low frequency and D/A does not start
-if I use a sine tone generator in sigma dsp with e.g. 10kHz signal, the output on the D/A is 5kHz; alwas halfe!
I attached my project. Any ideas? Now trying for 2 days and about giving up...