ADAU1466 Synchronous Sample Rate Conversion (48kHz to 96kHz) the Hard Way

Let's say I have an I2S source (ADC) at 48kHz and I want to run my ADAU1466 DSP filters at 96kHz and I want the output I2S serial port (DAC) to run at the same 96kHz.  The MCLK is synchronous to the ADC, DSP, and DAC (phase is unknown but constant).  The easy solution is to just use the internal ASRCs and call it a day, but let's say I enjoy suffering and I want to do my own synchronous sample rate converter with a self-designed FIR interpolation filter.  What's the procedure in SigmaStudio to up-sample the ADC serial port by 2 (inserting 0 every other sample) from 48kHz to 96kHz?  Is it as simple as letting the ADC clock the LRCLK_IN0 synchronously to the DSP at 48kHz and using the up-sample by 2 block in SigmaStudio with my project configured for 96kHz processing?

Thanks for entertaining my question!

-Jesse

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  • +1
    •  Analog Employees 
    on Jun 3, 2021 6:52 PM

    Hi Jesse,

    It is really this simple but there are some traps that are easy to miss.

    If your clocks are configured correctly, the upsample module configured with x2 will do what you need. You will also have the option to choose the mechanism used (zero insertions or zero order hold) by right-clicking on the upsample module.

    You might need to manually set the sample rate of the slower input by right-clicking on it and using the dropdown menu. New cells match the project sample rate by default. You can check whether this worked by hovering the mouse over schematic wires; they will display the configured sample rate.

    Note that earlier versions of the Upsample module had a LPF Enable checkbox, but the LPF didn't work. You would need to add your own (usually FIR) antialiasing filter.

    Regards,

    Joshua

Reply
  • +1
    •  Analog Employees 
    on Jun 3, 2021 6:52 PM

    Hi Jesse,

    It is really this simple but there are some traps that are easy to miss.

    If your clocks are configured correctly, the upsample module configured with x2 will do what you need. You will also have the option to choose the mechanism used (zero insertions or zero order hold) by right-clicking on the upsample module.

    You might need to manually set the sample rate of the slower input by right-clicking on it and using the dropdown menu. New cells match the project sample rate by default. You can check whether this worked by hovering the mouse over schematic wires; they will display the configured sample rate.

    Note that earlier versions of the Upsample module had a LPF Enable checkbox, but the LPF didn't work. You would need to add your own (usually FIR) antialiasing filter.

    Regards,

    Joshua

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