When ASRC do not have any valid input signal (no clock at input, ASRC unlocked) it should go to mute and output a data of 0 no ?Instead ASRC outputs a continuous data value.
When ASRC is locked, if I manually set MUTE in register 0xF581, data are at 0. If I remove input signal, data remains to 0.When ASRC is locked, if I remove input signal without mute ASRC before, data seems to stay at last valid value even if I set manually the ASRC mute.
Any ideas where that could comes from ?
It is a result of the clocks going away and so the filter just stops. I do not know how the designers could have fixed this but at this point it does not matter. I have developed a fix for this in software. The other issue you might not have noticed is that when the part is powered up the ASRC data memories have random values and there is no way to clear it until clocks are present at the input. So if you power up with no clocks coming in it will output a random DC value and then there will be some noises for about 1 to 3 ms after clocks have been applied as the random numbers shift out of the memory.
So my software fix will handle both cases. If you do not have many MIPS left to do this then you can simply put in a DCblock cell on the ASRC signal. This will filter out any DC values. There will still be a pop when the data stops as the filter removes the DC.
I have attached the example project which shows how to mute the audio when the ASRX is not locked.
6087.ADAU1452 ASRC Lock Detect Example.zip
Thank you Dave for your answer.
It's a bit complicate to implement the patch directly in the DSP as we are not using internal blocks but routing directly ASRC to SDIN and SDOUT with registers.
We are polling for ASRC unlocked status and mute signal in the FPGA that is connected to SDOUT. It seems to do the job.
Do you know if this bug have been corrected in ADAU1466 ?