ADAU1467 MCLK routing

Hi,

I have 1 x ADAU1467 running using I2C from micro.

all of its ports are hooked up to hardware.

I have an 12.288mhz oscillator with 8 channel buffer driving XTALIN/MCLK pin on ADAU1467 and other hardware ( ADC's and DAC's etc )

I'm using the PLL clock to divide down bitclock's LRCLK etc 

as far as I understand the 12.288mhz MCLK is actually used for the ADAU1467 system clock with settings below in pic.

on a previous revision of my prototype this actually worked ( I think my DAC and ADC don't require a MCLK in phase , only needs to be synchronous , I'm assuming there is

delay by 1 frame on input MCLK and output LRCLK / BTCLK but did not check in the scope )

I have no way to switch from say 48khz to 44.1khz etc

I think I am write is saying it makes far more sense for me to output on pin 27 CLKOUT the generated MCLK to the 8 channel clock buffer and drive ADC / DAC hardware from that

My micro controller is hooked up to the DSP TDM lines and BCLK LRCLK in slave mode and doesn't need MCLK. Its more the ADC and DAC and CODEC hardware that requires it.

Hopefully someone here can reassure me i am understanding this ?

before I start cutting up my prototype board and adding the bodge wires :)



I have since learned i don't need to change the MCLK for ADC DAC hardware. But I am still not sure how to change FS of serial IO etc. see follow up question
[edited by: benybiles at 2:07 PM (GMT -4) on 25 Oct 2020]
  • Update:

    I scope probed CLKOUT and it has 12.288mhz as expected and I think a quarter of a clock late compared with

    input MCLK. so I can see it makes more sense to use this CLKOUT as would sync with bitclock LRCLK better.

    I changed the sigma studio project to 44.1khz and and CLKOUT was still 12.288mhz which I think makes sense.

    I get no captured register hex codes when I change FS circled in picture below.

    Can I use sigma studio to find the sequence of registers needed to change FS with microcontroller ?

    If I have to reset the DSP , do I need to load a large amount of reg settings for the DSP ?

    Or is it just a question of setting the clock generator to use in the serial ports?  in my case for 44.1khz FS clk gen 3 as in picture in 1st post above?

    I'd like to change the FS of the hole audio signal chain rather than use ASRC if that's possible?

  • I made the changes to the prototype and not CLKOUT feeds the 8xCLK buffer IC and then my other hardware.

    Working find and it seams like the MCLK is more synchronous with LRCLK and BCLK

    I hooked up the SigmaStudio USBi programmer pins on I2C to my prototype and can now make live changes.

    for some strange reason my DAC wans FS*2 to work without noise.

    I can change the individual serial port clock sources and I get clean audio repitched.

    I think I need to fix the DAC clock requiring *2 FS and then I can change the sample rate on each serial port changing the FS multiplier or divider and change clock source for the 44.1khz

    I think I resolved this issue as far as the DSP goes.

  • 0
    •  Analog Employees 
    on Oct 26, 2020 3:14 PM 1 month ago in reply to benybiles

    Hello benybiles,

    I do not think I will be able to answer all your questions in this one reply. You asked a lot of questions and make a lot of comments, but I will give it a shot. 

    The FS setting at the top of SigmaStudio will not send anything to the DSP. It does not change the sample rate of the DSP. The DSP rate is determined by register settings and the actual clocks applied to the DSP. SigmaStudio has no idea what that actually is. What the setting is for is to tell the complier what the desired fs is so it can calculate the filter coefficients and set the parameters correctly for blocks that need timing information. Things like oscillators and compressor cures etc. So if you set this to 48kHz but are running the DSP at 44.1kHZ then the filter cures will be off in frequency as will anything else that needs timing info. So if you are going to change sample rates and do not want to use the ASRCs, then you will need to load in a different version of the program. 

    The master clock timing between the MCLK in pin and the CLKOUT pin is because the CLKOUT pin is the output of the PLL so it will be slightly different. Yes, most of our codecs only need X transitions of MCLK and the phase relationship of the MCLK edges to the LRCLK edges are not important. You are correct to use the CLKOUT pin if a device is more stringent in its requirement for master clock. 

    If you need to run at 44,1kHz AND you need to use the CLKOUT to be at this different rate then you will need to change the master clock source. Although, there is another option. You can setup Clock Gen 1 to put out multiples of 44.1kHz and then setup an unused serial port to put out 11.2896MHz out of a Bit Clock pin. If you are using TDM8 then you will already have one setup to do this. Then distribute that to the other parts. It is a common practice to use the bit clock to drive the serial port and master clock of a slave device. 

    For the 2*fs clock requirement. If you have an extra serial port then set that one up for fs*2. It could be an input or output port since the internal clocks are the same. 

    Dave T