ADAU1467 MCLK routing

Update:

I scope probed CLKOUT and it has 12.288mhz as expected and I think a quarter of a clock late compared with

input MCLK. so I can see it makes more sense to use this CLKOUT as would sync with bitclock LRCLK better.

I changed the sigma studio project to 44.1khz and and CLKOUT was still 12.288mhz which I think makes sense.

I get no captured register hex codes when I change FS circled in picture below.

Can I use sigma studio to find the sequence of registers needed to change FS with microcontroller ?

If I have to reset the DSP , do I need to load a large amount of reg settings for the DSP ?

Or is it just a question of setting the clock generator to use in the serial ports?  in my case for 44.1khz FS clk gen 3 as in picture in 1st post above?

I'd like to change the FS of the hole audio signal chain rather than use ASRC if that's possible?

I made the changes to the prototype and not CLKOUT feeds the 8xCLK buffer IC and then my other hardware.

Working find and it seams like the MCLK is more synchronous with LRCLK and BCLK

I hooked up the SigmaStudio USBi programmer pins on I2C to my prototype and can now make live changes.

for some strange reason my DAC wans FS*2 to work without noise.

I can change the individual serial port clock sources and I get clean audio repitched.

I think I need to fix the DAC clock requiring *2 FS and then I can change the sample rate on each serial port changing the FS multiplier or divider and change clock source for the 44.1khz

I think I resolved this issue as far as the DSP goes.

Hello benybiles,

I do not think I will be able to answer all your questions in this one reply. You asked a lot of questions and make a lot of comments, but I will give it a shot. 

The FS setting at the top of SigmaStudio will not send anything to the DSP. It does not change the sample rate of the DSP. The DSP rate is determined by register settings and the actual clocks applied to the DSP. SigmaStudio has no idea what that actually is. What the setting is for is to tell the complier what the desired fs is so it can calculate the filter coefficients and set the parameters correctly for blocks that need timing information. Things like oscillators and compressor cures etc. So if you set this to 48kHz but are running the DSP at 44.1kHZ then the filter cures will be off in frequency as will anything else that needs timing info. So if you are going to change sample rates and do not want to use the ASRCs, then you will need to load in a different version of the program. 

The master clock timing between the MCLK in pin and the CLKOUT pin is because the CLKOUT pin is the output of the PLL so it will be slightly different. Yes, most of our codecs only need X transitions of MCLK and the phase relationship of the MCLK edges to the LRCLK edges are not important. You are correct to use the CLKOUT pin if a device is more stringent in its requirement for master clock. 

If you need to run at 44,1kHz AND you need to use the CLKOUT to be at this different rate then you will need to change the master clock source. Although, there is another option. You can setup Clock Gen 1 to put out multiples of 44.1kHz and then setup an unused serial port to put out 11.2896MHz out of a Bit Clock pin. If you are using TDM8 then you will already have one setup to do this. Then distribute that to the other parts. It is a common practice to use the bit clock to drive the serial port and master clock of a slave device. 

For the 2*fs clock requirement. If you have an extra serial port then set that one up for fs*2. It could be an input or output port since the internal clocks are the same. 

Dave T

Hi Dave , thanks so much for taking the time to explain this.

I rewired my prototype to receive 12.288mhz oscillator on XTALIN/MCLK pin on adau1467 and then I drive the clock 8 chan clock buffer from DSP CLKOUT which drives CS5386 ( 8chan ADC ) and CS4385 ( 8 channel DAC ) in slave mode. The SAI ports on ARM micro slave to the ADAU1467 without the need for MCLK.

It seams I fixed the 2x FS problem by setting ADAU1467 DSP LRCLK to pulse on the ADC input. there was a small APP note for CS5386 hidden away recommending pulse mode for TDM8 slave mode. Not quite sure why they don't just put that in the datasheet.

The audio inputs are clean sounding now for at least 5mins the the adc gets hot 5 - 10mins time and then pink noise appears again from the ADC.

Looks like this is an electrical design fault on my ADC DAC card. I skipped the input buffers on the analogue ADC inputs only using DC blocking caps from the preamps. could be that or maybe my ADC DAC card is just to small and it's just over heating.

I'll try making different adau1467 code for different sample rates and reboot the DSP from the micro if I need to change recording FS mode. If i need to change MCLK on the slaved devices I think I can just use PLL and output it from CLKOUT now.