I have 1 x ADAU1467 running using I2C from micro.
all of its ports are hooked up to hardware.
I have an 12.288mhz oscillator with 8 channel buffer driving XTALIN/MCLK pin on ADAU1467 and other hardware ( ADC's and DAC's etc )
I'm using the PLL clock to divide down bitclock's LRCLK etc
as far as I understand the 12.288mhz MCLK is actually used for the ADAU1467 system clock with settings below in pic.
on a previous revision of my prototype this actually worked ( I think my DAC and ADC don't require a MCLK in phase , only needs to be synchronous , I'm assuming there is
delay by 1 frame on input MCLK and output LRCLK / BTCLK but did not check in the scope )
I have no way to switch from say 48khz to 44.1khz etc
I think I am write is saying it makes far more sense for me to output on pin 27 CLKOUT the generated MCLK to the 8 channel clock buffer and drive ADC / DAC hardware from that
My micro controller is hooked up to the DSP TDM lines and BCLK LRCLK in slave mode and doesn't need MCLK. Its more the ADC and DAC and CODEC hardware that requires it.
Hopefully someone here can reassure me i am understanding this ?
before I start cutting up my prototype board and adding the bodge wires :)
I have since learned i don't need to change the MCLK for ADC DAC hardware. But I am still not sure how to change FS of serial IO etc. see follow up question
[edited by: benybiles at 2:07 PM (GMT -4) on 25 Oct 2020]