ADAU1466 192k Sampling

I am trying to setup the clock control for 192k sampling.  In this case I need the MCLK OUT to be Base_Fs x 256 (12.288 MHz).  I am using CLK GEN1.  Currently I have the PLL CTRL1 to Divide by 8 and the PLL CTRL0 set to 96.  In this case it seems that the CLK GEN1 needs to be N=1 and M=1.  

I am testing this on the ADAU1466 dev board using the optical in and optical out.  I am unable to lock to the output port with the above settings.  It will work in the case of 96k if N=1 and M=3.  I can also get 192k to work when I use Base_Fs x 512 (24.576Mhz) with N=1 and M=3

Is it not possible to do 192k sampling with Base_Fs x 256?