my system consists of an ADAU1467 and two PCM3168A codecs, for a total of 8 inputs (4 on each codec) and 16 outputs (8 on each codec).
DSP and CODECS receive both the master clock from a 24.576 MHz external oscillator.
The DSP is BCLK and LRCLK master: it receives and transmits digital audio @96kHz in TDM4 format, using Serial Input Port 0 and Serial Output Port 0, using the following audio digital data lines:
Running a simple DSP application that performs just a input - output routing of the first 8 channels (see the attached project),
- inputs 1 - 4 are faithfully reproduced on the corresponding outputs: if no signal is applied on the input, the outputs are silent and everything works correctly
- inputs 5 - 8 generates the following noise (I took the signal from the analog outputs of the CODEC 1)
I stated it depends on the inputs because if I route input 1 - 4 to output 1 - 4 and 5 - 8 all outputs works fine.
i did a lot of tests before writing here, I'm pretty sure the problem is not in my board layout / schema / power, but it depends on the DSP.
Any suggestion would be really appreciated.
This is looking like a timing issue.
Try to increase the drive strength of the clock outputs on serial input port 0 to maximum. This may help. Since the SDATAIO pin is an input you do not…
Try to increase the drive strength of the clock outputs on serial input port 0 to maximum. This may help. Since the SDATAIO pin is an input you do not need to change that register.
The project you attached has the fs setup for 96kHz by adjusting the Clock Gen 1 to be 2/6. Now this is correct but I have recently seen problems where someone had set this up to be 192kHz and there were some issues. So try to set it back to the default 1/6 and then select the fs*2 settings where you need it.
Running a serial input port as a master is the worst configuration from a standpoint of timing of the data verses the bitclock. The bitclock has to leave the DSP and travel to the ADC. Then the ADC needs to detect the edge of the bitclock and instruct the serial port to output the next bit of data. Then that data has to travel back to the DSP in time for the rising edge of the bitclock to latch in the data. When running at higher bitclock rates this gets to be more difficult to meet the timing margins. TDM4 at 96kHz is not the worst case but it is still 12.288MHz. Since they are all getting the same master clock I would consider changing the ADC part of the codec to be a master. The DACs should be a slave. Basically, the best setup is to have the device that is sending the data also send the clocks. Then all the signals are pretty much all delayed by the same amount. I do not know if this codec can have the ADC be a master and the DAC be a slave. I know our AD1938/39 codec can do that.
I am wondering if it would be possible at this late date to change how you are using the serial ports. It would be better to put the two TDM 4 signals onto two ports on their own and then use one of the other ports for two I2S signals and the last port for one I2S signal. I did see that two of them are being clocked from the DSP.