ADAU1467 does not boot up properly

I'm working on a board with an ADAU1467 acting as an audio processor, and programmed with SigmaStudio 4.5. I'm currently stuck with a weird bug where I have several boards that will not program. As in, I'll run the link-compile-download sequence and the chip will not respond. Reading from the DSP registers gives me either a string of 0x00s or 0xFFs. I do not see any activity on the CLKOUT pin, even though I have a 12.288MHz crystal supplying a valid MCLK signal. Looking at the datasheet for the ADAU1467, it seems like the device is not booting up properly, perhaps the PLL is not locking and causing the control port to be held in reset (from page 26 of the datasheet).

I've probed the voltage rails and they all seem fine:

IOVDD: 3.3V

AVDD: 3.3V

PVDD: 3.3V

DVDD: 1.2V

VDRIVE: 2.72V

Here's a link to the DSP portion of my schematic, it's too big to fit into this post: https://i.imgur.com/hVk9kcg.png

What could be causing the chip to not boot up? Is there anything else I can probe or provide?

It's worth noting that 3 out of the 10 boards in this production batch seemed to work properly right away. I was able to salvage a few other boards by replacing the ADAU1467 with a fresh chip. A previous version of this board (with the exact same schematic and BOM) had 9 of the 10 boards program and boot properly.

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  • 0
    •  Analog Employees 
    on Sep 3, 2020 8:23 PM 5 months ago

    Hello aytil,

    I was not able to see the schematic. 

    The CLKOUT pin may or may not output a signal, it depends on the register settings. 

    Are you using SPI or I2C to communicate to the DSP?

    For the comms port to function, and read or write registers, all you need is master clock on the MCLK pin. As long as the SPI or I2C clock does not exceed the MCLK frequency, it will work. It does not need the core to be working or a program loaded. Once the PLL locks then you can communicate up to full speed. 

    What is your reset circuit?

    Dave T

  • I'm using a SPI interface, I haven't checked the clock frequency but it's definitely lower than the 12.228MHz crystal supplying the MCLK.

    I have the reset pin tied directly to 3.3V (IOVDD). In hindsight I should have added a button or jumper but the datasheet says the chip is designed to boot with the reset pin tied high.

    How can I check if the PLL is locked?

    Here's the schematic:

  • 0
    •  Analog Employees 
    on Sep 8, 2020 6:50 PM 5 months ago in reply to aytli

    Hello aytil,

    To know that the PLL is locked you simply read the PLL lock register. It does not need to have the PLL locked to read and write to memory. So since you cannot read any register then something is up that is more basic. Either the wiring on the SPI port is wrong, or there is a power issue. 

    The reset pin is something to look into. I usually see at least an RC filter on the reset pin to filter out the noise and also to slightly delay the reset releasing until the power has gone up for a short time. It is best to actually use a reset generator to hold the reset down for a period of time, 200ms-ish, before releasing it. 

    So I would look into that. Also make sure the power rails are coming up in the correct order. That said, since you are using the internal regulator for DVDD it is somewhat difficult to get this wrong. The AVDD and IOVDD should come up around the same time. 

    So look into the reset issue, then look closely at the power and then look at the SPI communication. 

    Dave T

  • Thanks for the response. I scoped the voltage rails and got the waveform below.

    Yellow = IOVDD (3.3V-D)

    Blue = PVDD

    Purple = AVDD

    Green = DVDD, starts rising about 80ns after the other rails.

    It seems like DVDD starts rising when the other 3 rails are around 2V, before they reach steady state. Could this be causing issues with the reset circuitry? Is there a way to delay start of the internal DVDD regulator?

    EDIT:

    I was able to cut a trace to disconnect the reset pin from IOVDD and solder a piece of magnet wire onto the reset pin. I pulled the reset pin to IOVDD through a 10k resistor, then connected it to GND through a button. On startup, the chip will still not program properly. Once I press the button (shorting reset to GND), the chip programs properly.

    I then added a 10uF capacitor between the reset pin and GND to slow down the rise time on startup, and the chip seemed to boot properly every time. Below is a picture of the final reset circuitry.

    Thanks for your help!

  • Hi, we are just finishing a project with 2 sigmadsp in dual mono and we observed that it was absolutely not possible to use the standard USBi interface in SPI mode due to the fact that it generates MODE 0 SPI frames instead of the expected MODE 3 ! 

    the fact is that some simple parasitic capacitor across the SPI pins can t make the MODE to work on a MODE 3 device !. this is something we were able to reproduce on a ADAU1452 official evaluation board and with the USBi. putting extra wires around like for connecting a small salae analyzer did destroy the whole communication, despite the salae showing proper sequence sent in MODE 0.

    MODE 3 is a key point for making your SPI stuff working.

    We got 100% immediate success with a microcontroler using the Sigmastudio.h files and SPI MODE 3.

    Second trick. We noticed that when you write PLL_ENABLE to 1 or START_CORE, you get significant consumption on the IOVDD and DVDD which might generate an HW reset from your local ADM811 or PSU monitoring system !

    One way to capture this was to set PLL_CTRL0 to 95 instead of 96 and monitor it along the program test. if it goes back to 96 the you got an HW reset !

    good luck, this is a fantastic chip but be very polite with it

  • 0
    •  Analog Employees 
    on Sep 15, 2020 12:22 AM 5 months ago in reply to fabriceo

    The Mode 0 vs Mode 3 issue is described here, and to our knowledge this is not really an issue at all.

    It's not recommended to change the PLL feedback divider like this. Changing the PLL divider from 96 to 95 will change both the DSP core rate and the audio sample rate if you aren't careful.

    There are plenty of other system registers you could use for this purpose; for example, an I2S vs. TDM setting for an unused serial port. Or, if you aren't specifically using clock gen 3, the N and M generally won't affect anything else.

    Or, and this is what I would recommend, monitor the logic levels on the RESET and DVDD pins.

  • 0
    •  Analog Employees 
    on Sep 15, 2020 1:15 AM 5 months ago in reply to fabriceo

    I would like to add one more thing.

    If the ADM811 (or other PSU monitoring system) is triggering a reset when the START_CORE bit is toggled, this indicates a problem in the power delivery system.

    A reset generator like the ADM811 toggles reset if the supply voltage goes below its comparator threshold.

    If your power supply is appropriately sized (adequate current capacity) and bypass capacitors are properly connected, in the correct locations, the power supply voltage should never drop so low to trigger RESET.

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  • 0
    •  Analog Employees 
    on Sep 15, 2020 1:15 AM 5 months ago in reply to fabriceo

    I would like to add one more thing.

    If the ADM811 (or other PSU monitoring system) is triggering a reset when the START_CORE bit is toggled, this indicates a problem in the power delivery system.

    A reset generator like the ADM811 toggles reset if the supply voltage goes below its comparator threshold.

    If your power supply is appropriately sized (adequate current capacity) and bypass capacitors are properly connected, in the correct locations, the power supply voltage should never drop so low to trigger RESET.

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