ADAU1401 MCLK and BCLK

I am currently working on a project with the adau1401. I going to be using an spdif receiver connected to an ASRC and then to the ADAU1401. The ADAU1401 will be doing some filtering and outputting i2s to a set of three DACs. I'm having an issue conceptually. So, if the ADAU1401 is the master, then the BCLK pin will be outputting the MCLK rather than the BCLK and I need to find a way to create the BCLK? Or, would it be better to have an external clock generator create the master clock and the ADAU1401 will not be the master device?

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  • I am currently looking at using the cs8421 from cirrus logic. Was also wondering if I could just use a clock generator rather than a pll to generate a fixed MCLK if the sampling frequency is fixed?

  • +1
    •  Analog Employees 
    on May 20, 2020 7:28 PM 10 months ago in reply to Scorch

    Hello Scorch,

    We have used the CS8416 and it has a clock output which is 128x fs or 256 x fs once the PLL locks to the incoming signal. It also will also switch to a system clock if the PLL is not locked. 

    This is what should drive the master clock input of the DSP. 

    I did not look at the CS8412 but it looks like CopperMaze did. The key is you have to have a master clock that is derived from the incoming clock on the SPDIF signal. Then you will not need a sample rate converter because the DSP will just follow the sample rate of the incoming SPDIF signal. 

    The only problem is if you are planning on using higher sample rates above 48kHz. Then it starts getting tricky. 

    I also recommend you move to the ADAU145x family of parts with SPDIF and ASRCs built in. They are so much more powerful and you can do a lot more with them without the need of a controller. 

    Dave T

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  • +1
    •  Analog Employees 
    on May 20, 2020 7:28 PM 10 months ago in reply to Scorch

    Hello Scorch,

    We have used the CS8416 and it has a clock output which is 128x fs or 256 x fs once the PLL locks to the incoming signal. It also will also switch to a system clock if the PLL is not locked. 

    This is what should drive the master clock input of the DSP. 

    I did not look at the CS8412 but it looks like CopperMaze did. The key is you have to have a master clock that is derived from the incoming clock on the SPDIF signal. Then you will not need a sample rate converter because the DSP will just follow the sample rate of the incoming SPDIF signal. 

    The only problem is if you are planning on using higher sample rates above 48kHz. Then it starts getting tricky. 

    I also recommend you move to the ADAU145x family of parts with SPDIF and ASRCs built in. They are so much more powerful and you can do a lot more with them without the need of a controller. 

    Dave T

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