ADAU1401 MCLK and BCLK

I am currently working on a project with the adau1401. I going to be using an spdif receiver connected to an ASRC and then to the ADAU1401. The ADAU1401 will be doing some filtering and outputting i2s to a set of three DACs. I'm having an issue conceptually. So, if the ADAU1401 is the master, then the BCLK pin will be outputting the MCLK rather than the BCLK and I need to find a way to create the BCLK? Or, would it be better to have an external clock generator create the master clock and the ADAU1401 will not be the master device?

Parents
  • ADAU1401 serial audio input => LRCLK and BCLK are "slave" only. (datasheet p.46).

    I see some options:

    - Generate MCLK with a dedicated chip and push that into both the ASRC and the ADAU1401, and use the ASRC to generate BCLK and LRCLK.

    - Generate all the clocks needed between ASRC and ADAU on a dedicated clock generator chip (including MCLK).

    - Use an ASRC with PLL able to generate its own MCLK from BCLK, and get BCLK and LRCLK from the ADAU1401 output. ADAU is making MCLK with an Xtal in this case.

Reply
  • ADAU1401 serial audio input => LRCLK and BCLK are "slave" only. (datasheet p.46).

    I see some options:

    - Generate MCLK with a dedicated chip and push that into both the ASRC and the ADAU1401, and use the ASRC to generate BCLK and LRCLK.

    - Generate all the clocks needed between ASRC and ADAU on a dedicated clock generator chip (including MCLK).

    - Use an ASRC with PLL able to generate its own MCLK from BCLK, and get BCLK and LRCLK from the ADAU1401 output. ADAU is making MCLK with an Xtal in this case.

Children
No Data