Looking at the ADAU1701 datasheet, page 28 under writeback section, I understand that I need to keep the power supply "alive" for 73usec in order to complete a safe writeback:
"The maximum number of bytes that is written back from the ADAU1701 is 35 (eight 4-byte interface registers plus three bytes of EEPROM-addressing overhead). With SCL running at 384 kHz, the writeback operation takes approximately 73 μs to complete after being triggered. Ensure that sufficient power is available to the system to allow enough time for a writeback to complete, especially if the WB signal is triggered from a falling power supply voltage."
But If I do the calculation, I think there is a mistake
If the SCL frequency is 384KHz, so one bit duration is 1/384,000 = 2.604usec
So, 35 bytes takes 35*8*2.604usec to write, and this is equal to 730usec, and not 73usec as mentioned.
I wanted to check the writeback procedure duration using the EVAL-ADAU1701MINIZ (after modifying the writeback transistor trigger so that it will actually work...)
I probed the EEPROM SCL pin, while disconnecting the main power supply:
I could clearly see that the writeback duration is about 824usec, that is more closer to 730usec than 73usec...
Is this correct?
[edited by: Nir76 at 11:26 PM (GMT 0) on 7 May 2020]