ADAU1701 - BCLK & LRCLK Distribution

Hello all,

Following my last post: 

https://ez.analog.com/dsp/sigmadsp/f/q-a/164350/adau1401a---connecting-external-slave-mode-codecs

I assembled this setup using the EVBs of the ADAU1701 and the external codecs.
I wanted to check if this configuration works even without the use of fanout buffers:
Actually, the series terminations were also not assembled. I used star connections for the BCLK & LRCLK, with different wires lengths.
Even with this simplest implementation, the setup works well (setup functionality only, not signal integrity wise...) 
For the final circuit, I do intend to add serial terminations, and to have control impedance and matched traces lengths for all of the I2S buses.
My question is:
Where can I find information regarding the:
1- Maximum allowed C-Load of the BCLK, LRCLK as output ports? 
2- Maximum input capacitance of BCLK, LRCLK as input ports? (As mentioned, the ADAU1701 is also clocking its own inputs)
Other than the setup is working well,I have no way of knowing if I'm overloading the BCLK, LRCLK lines.
Thanks for helping,
Best Regards,
Nir


.
[edited by: Nir76 at 11:14 AM (GMT 0) on 2 May 2020]