ADAU1701 - BCLK & LRCLK Distribution

Hello all,

Following my last post:

I assembled this setup using the EVBs of the ADAU1701 and the external codecs.
I wanted to check if this configuration works even without the use of fanout buffers:
Actually, the series terminations were also not assembled. I used star connections for the BCLK & LRCLK, with different wires lengths.
Even with this simplest implementation, the setup works well (setup functionality only, not signal integrity wise...) 
For the final circuit, I do intend to add serial terminations, and to have control impedance and matched traces lengths for all of the I2S buses.
My question is:
Where can I find information regarding the:
1- Maximum allowed C-Load of the BCLK, LRCLK as output ports? 
2- Maximum input capacitance of BCLK, LRCLK as input ports? (As mentioned, the ADAU1701 is also clocking its own inputs)
Other than the setup is working well,I have no way of knowing if I'm overloading the BCLK, LRCLK lines.
Thanks for helping,
Best Regards,

[edited by: Nir76 at 11:14 AM (GMT 0) on 2 May 2020]
  • +1
    •  Analog Employees 
    on May 4, 2020 8:29 PM

    Hello Nir,

    1) I do not have that information and it would be very difficult to try to find this information this long after the part was designed. 

    2) The input capacitance of the digital pins is in the datasheet. 5pf max. So that is some information. Often we have iBIS models for our parts but this part was designed and released before we started having the iBIS models made. So I am afraid I am not of much help here. 

    It is not likely you will be damaging any of the BCLK or LRCLK pins, since you are not trying to drive a short and most parts can handle a fanout of more than three.  If you look at the scope and see that it is not able to drive the load with your test then I would be concerned. Your test is sort of a worst case with no damping resistors so if there is too much capacitance your rise time will be slow. If your test looks good then I think you are fine since your design will end up with some damping resistors. 

    Look at the scope and run the system at the highest sample rate you will be using and then see what the timing margin is between the BCLK and SDATA. That will be another good test. 

    Dave T

  • Hi Dave,

    I did some actual measurements and you are right - the clock pins can handle a fanout of four part (including the ADAU1701 itself).

    When the ADAU1701 BCLK is not connected to any load, the waveform looks like this: (Using an active probe with 1pF capacitance)

    The BCLK is 3.072MHz, rise and fall time are about 6nsec, the signal BW is about 0.35/6nsec = 58MHz

    When the ADAU1701 BCLK is connected to four loads, the waveform looks like this:

    In this condition, rise and fall time are about 14nsec. the signal BW was reduced to about 0.35/14nsec = 25MHz

    Still, 25MHz of BW can transfer 5 harmonics of the clock square wave...

    The signal looks clean, no over/undershoots. the extra capacitance did caused the rise/fall time to increase, but this is understandable. 

    I remind you that this measurement is with no termination resistors or solid ground plane underneath the signal, so in the final PCB things should even get better. 

    Thanks again for your kind help.


  • 0
    •  Analog Employees 
    on May 12, 2020 10:54 PM in reply to Nir76

    Hello Nir,

    These signals look really good so that is good news. You should be able to proceed with your tests 

    Dave T

  • Hi Dave,

    Thanks for replying to my last posts!

    In order complete the hardware design, I have another question regarding not connected pins.

    In my design, I'm using only the digital ports, no ADCs or DACs

    Can I leave all the ADC/DAC pin unconnected?

    I'm referring to these pins:

    1- ADC0,1

    2- VOUT0,1,2,3


    5- ADC_RES

    6- CM

    Thanks again!

    Best Regards,


  • +1
    •  Analog Employees 
    on May 14, 2020 5:30 PM in reply to Nir76

    Hello Nir,

    You may be able to power down some of these sections if you are also not using the AUXADCs. But to be safe I would put these components into the design and don't populate them later if they are not needed. 

    The FiltA, FiltD and the CM pins you still should bypass to keep the references from oscillating and causing problems in the part. 

    You should include the ADC_RES for the same reason. 

    The ADC in is a good idea to cap couple to ground. You can directly ground it but it will draw some current due to the CM bias. You do not need a huge cap. 10uf will be great but you could probably get away with 4.7uf or 2.2uf. 

    The DAC outputs can be left floating. If you feel you have to terminate them then use a 10K to ground. 

    Then experiment with the board. Shut off power to the ADCs and DACs and shut off the internal reference supply. Then see if the part works and there is no voltage on the CM and FILTx pins. What I am concerned about is that some of these older parts had some strange "bugs" in that shutting down some sections of the parts would cause other sections not to function. So this is why I am saying to design in the parts then experiment with it afterwards if possible. 

    I could experiment here if I have time but that might not be for a while, 

    Dave T