In my project, I'm using the EVAL-ADAU1467Z to evaluate the DSP.
The codec included on the EVB, has separate, one-way ports for the input and output signals:
I plan to use a codec with a single I2S bidirectional port (BCLK, LRCLK, DATA IN, DATA OUT lines).
How should I configure/connect the LRCLK_IN, BCLK_IN pins?
The way I see it, there are three options:
1- Codec in slave mode, and the DSP will in master mode:
2- Codec in slave mode, and the DSP in master mode:
3- Codec in master mode, and the DSP in slave mode:
What is the right way to do it?
Configuration 1: This will work. Since the DSP is generating BCLK and LRCLK, you can declare both interfaces as clock master and leave LRCLK_IN0 and BCLK_IN0 unconnected. You can use the unused…
Actually, configuration 1 is the one that I've tested, and yes, it worked just fine.
I was a bit strange to leave the BCLK_IN0, LRCLK_IN0 (configured as master) unconnected, and I was just…
Configuration 1: This will work. Since the DSP is generating BCLK and LRCLK, you can declare both interfaces as clock master and leave LRCLK_IN0 and BCLK_IN0 unconnected. You can use the unused clock pins as GPIO if you want.
Configuration 2: This will work, but since the DSP is generating BCLK and LRCLK it is not required to make the connection from LRCLK_OUT0 to LRCLK_IN0 or from BCLK_OUT0 to BCLK_IN0. If you do make these connections, either the input port or the output port should be declared a clock slave to avoid contention.
Configuration 3: This will work as long as the CODEC and DSP receive the same master clock (which on the ADAU1467 eval board, they do). Since the DSP serial ports are operating in slave mode, you will need to connect BCLK and LRCLK to both the input port and the output port. If the CODEC and DSP do not receive the same master clock you may wish to use an ASRC.
Note that if the AD1937 CODEC is in standalone mode it will boot up as a clock slave and you will want to use Configuration 1 or 2. Also, on the evaluation board, you will need to use the SDATAIO pins to access the second pair of input channels, and the last 3 pairs of output channels.
I hope this is helpful.
I was a bit strange to leave the BCLK_IN0, LRCLK_IN0 (configured as master) unconnected, and I was just making sure that I'm not doing something wrong.
If configuration 1 is OK, so I will use it because it's the most simple one (Board design wise...)
At first, I have used the EVB Codec, but later on I removed it in order to connect the serial port as I wish.
It's too bad that the EVB does not include an option to make any external interfaces between the DSP and the codec
But...2 minutes using a hot air gun did the job.
Thanks for your reply, You've been very helpful!
I just want to add one small thing to this discussion.
The codec, the AD1938, AD1937, AD1939 in standalone mode has the ability to have the ADC section be a slave or master. The COUT/SDA pin will select the master or slave mode. If the design needs to use a higher sample rate like 192kHz or a TDM8 or higher then running the ADC as a master will help with the timing margins for the data verses the bitclock.