AD1939 CODEC sample rate

For the AD1939 CODEC, data sheet specifies sample rates of 128/176.4/192 kHz if you set control register to '10'.  We did that and are at 192 kHz.  How do we get 128 kHz instead ?  That's the ADC/DAC sample rate we really want.  Thanks.

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  • +1
    •  Analog Employees 
    on Mar 26, 2020 3:10 PM 11 months ago

    Hello DKF638.

    Notice that for each setting there are three sample rates shown.

    32/44.1/48kHz

    64/88.2/96kHz

    128/176.4/192kHz

    Note that this register setting only adjusts a divider to divide the master clock.

    So here is the list again but with the divider added that divides down from the master clock.

    32/44.1/48kHz, MCLK divided by 256

    64/88.2/96kHz, MCLK divided by 128

    128/176.4/192kHz, MCLK divided by 64

    So which of the three sampling rates you get depends on the master clock rate. 

    If you use a 12.288MHz master clock then the three register settings will give you 48, 96, or 192kHz fs.

    So you will need to change the master clock to be 128 x 64 = 8.192MHz. 

    This is still within the range of the PLL so all you need to do is change the crystal to an 8.192MHz crystal ( or change the master clock source ) and you will be running at 32, 64 or 128kHz sampling rates. 

    Dave T

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  • +1
    •  Analog Employees 
    on Mar 26, 2020 3:10 PM 11 months ago

    Hello DKF638.

    Notice that for each setting there are three sample rates shown.

    32/44.1/48kHz

    64/88.2/96kHz

    128/176.4/192kHz

    Note that this register setting only adjusts a divider to divide the master clock.

    So here is the list again but with the divider added that divides down from the master clock.

    32/44.1/48kHz, MCLK divided by 256

    64/88.2/96kHz, MCLK divided by 128

    128/176.4/192kHz, MCLK divided by 64

    So which of the three sampling rates you get depends on the master clock rate. 

    If you use a 12.288MHz master clock then the three register settings will give you 48, 96, or 192kHz fs.

    So you will need to change the master clock to be 128 x 64 = 8.192MHz. 

    This is still within the range of the PLL so all you need to do is change the crystal to an 8.192MHz crystal ( or change the master clock source ) and you will be running at 32, 64 or 128kHz sampling rates. 

    Dave T

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